參數(shù)資料
型號： MT48LC32M4A2P-7ELIT:G
元件分類： DRAM
英文描述： 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁數(shù)： 30/74頁
文件大?。?/td> 2385K
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
36
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
PRECHARGE
The PRECHARGE command (see Figure 26) is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (tRP) after the PRECHARGE command is issued.
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Figure 26:
PRECHARGE Command
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (tREF or tREFAT) since no REFRESH operations are
performed in this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 27 on page 37.
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
DON’T CARE
HIGH
All Banks
Bank Selected
A0–A9
BA0, BA1
BANK
ADDRESS
VALID ADDRESS
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