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參數(shù)資料
| 型號： | MT48LC32M4A2P-7ELIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 31/74頁 |
| 文件大?。?/td> | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
37
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
Figure 27:
Power-Down
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 28 and Figure 29 on page 38.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Figure 28:
Clock Suspend During WRITE Burst
DON’T CARE
tRAS
tRCD
tRC
All banks idle
Input buffers gated off
Exit power-down mode
(
)
(
)
(
)
(
)
(
)
(
)
tCKS
> tCKS
COMMAND
NOP
ACTIVE
Enter power-down mode
NOP
CLK
CKE
(
)
(
)
(
)
(
)
DON’T CARE
DIN
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
n
NOP
CLK
T2
T1
T4
T3
T5
T0
CKE
INTERNAL
CLOCK
NOP
DIN
n + 1
DIN
n + 2
TRANSITIONING DATA
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT48LC32M4A2TG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
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