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參數(shù)資料
| 型號(hào)： | MT48LC32M4A2P-7ELIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 22/74頁 |
| 文件大?。?/td> | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
29
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 15
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 16 shows the case where the additional NOP is
needed.
Figure 15:
READ-to-WRITE
Notes:
1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-
mand may be to any bank. If a burst of 1 is used, then DQM is not required.
Figure 16:
READ-to-WRITE with Extra Clock Cycle
Notes:
1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-
mand may be to any bank.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
DON’T CARE
READ
NOP
WRITE
NOP
CLK
T2
T1
T4
T3
T0
DQM
DQ
DOUT n
COMMAND
DIN b
ADDRESS
BANK,
COL n
BANK,
COL b
DS
tHZ
t
tCK
TRANSITIONING DATA
DON’T CARE
READ
NOP
DQM
CLK
DQ
DOUT n
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
DIN b
BANK,
COL b
T5
DS
tHZ
t
TRANSITIONING DATA
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| MT48LC32M4A2TG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
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