參數資料
型號： MT48LC32M4A2P-7ELIT:G
元件分類： DRAM
英文描述： 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁數： 5/74頁
文件大?。?/td> 2385K
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
13
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Pin/Ball Descriptions
Table 4:
Pin/Ball Descriptions
54-Pin TSOP
54-Ball
VFBGA
60-Ball
FBGA
Symbol
Type
Description
38
F2
K2
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CLK. CLK also
increments the internal burst counter and controls the
output registers.
37
F3
L2
CKE
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW)
the CLK signal. Deactivating the clock provides
PRECHARGE power-down and SELF REFRESH operation
(all banks idle), ACTIVE power-down (row active in any
bank), or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device
enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode.
The input buffers, including CLK, are disabled during
power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
19
G9
L8
CS#
Input
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands
are masked when CS# is registered HIGH, but READ/WRITE
bursts already in progress will continue and DQM
operation will retain its DQ mask capability while CS# is
HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the
command code.
16, 17, 18
F9, F7, F8
J7, J8, K7
WE#,
CAS#,
RAS#
Input
Command inputs: WE#, CAS#, and RAS# (along with CS#)
define the command being entered.
39
–
J2
x4, x8:
DQM
Input
Input/Output mask: DQM is an input mask signal for write
accesses and an output enable signal for read accesses.
Input data is masked when DQM is sampled HIGH during
a WRITE cycle. The output buffers are placed in a High-Z
state (2-clock latency) when DQM is sampled HIGH during
a READ cycle. On the x4 and x8, DQML (pin 15) is a NC and
DQMH is DQM. On the x16, DQML corresponds to DQ0–
DQ7, and DQMH corresponds to DQ8–DQ15. DQML and
DQMH are considered same state when referenced as
DQM.
15, 39
E8, F1
–
x16:
DQML,
DQMH
20, 21
G7, G8
M8, M7
BA0, BA1
Input
Bank address inputs: BA0 and BA1 define to which bank
the ACTIVE, READ, WRITE, or PRECHARGE command is
being applied.
23–26, 29–
34, 22, 35
H7, H8, J8,
J7, J3, J2, H3,
H2, H1, G3,
H9, G2
N7, P8, P7,
R8, R1, P2,
P1, N2, N1,
M2, N8, M1
A0–A11
Input
Address inputs: A0–A11 are sampled during the ACTIVE
command (row-address A0–A11) and READ/WRITE
command (column-address A0–A9, A11 [x4]; A0–A9 [x8];
A0–A8 [x16]; with A10 defining auto precharge) to select
one location out of the memory array in the respective
bank. A10 is sampled during a precharge command to
determine whether all banks are to be precharged (A10
[HIGH]) or bank selected by BA0, BA1 (A10 [LOW]). The
address inputs also provide the op-code during a LOAD
MODE REGISTER (LMR) command.
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