參數(shù)資料
型號： MT48LC32M4A2P-7ELIT:G
元件分類： DRAM
英文描述： 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁數(shù)： 16/74頁
文件大小： 2385K
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
23
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Commands
A precharge of the bank/row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or WRITE burst, except in the
full-page burst mode, where auto precharge does not apply. Auto precharge is nonper-
sistent in that either it is enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in the “Operations”
section on page 24.
BURST TERMINATE
The BURST TERMINATE command is used either to truncate fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the “Operations” section on
The BURST TERMINATE command does not precharge the row; the row will remain
open until a PRECHARGE command is issued.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in older DRAMs. This command is nonpersistent, so
it must be issued each time a refresh is required. All active banks must be PRECHARGED
prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should
not be issued until the minimum tRP has been met after the PRECHARGE command as
shown in the operation section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. Regardless of device width, the
128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and
industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command
every 15.625s (commercial and industrial) or 3.906s (automotive) will meet the
refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO
REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once
every 64ms (commercial and industrial) or 16ms (automotive).
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain in self refresh mode for an
indefinite period beyond that.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48LC32M4A2TG 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM
MT48LC32M4A2TG-75 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM
MT48LC32M4A2TG-75IT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM
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