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參數(shù)資料
| 型號： | MT48LC32M4A2P-7ELIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 8/74頁 |
| 文件大?。?/td> | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
16
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Functional Description
7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again
or the device loses power. Not programming the mode register upon initialization will
result in default settings, which may not be desired. Outputs are guaranteed High-Z
after the LMR command is issued. Outputs should be High-Z already before the LMR
command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are
allowed.
At this point, the DRAM is ready for any valid command.
Note:
If desired, more than two AUTO REFRESH commands can be issued in the sequence.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH + tRFC loops is achieved.
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL),
an operating mode, and a write burst mode, as shown in Figure 7 on page 18. The mode
register is programmed via the LMR command and will retain the stored information
until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the BL, M3 specifies the type of burst (sequential or
interleaved), M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 speci-
fies the write burst mode, and M10 and M11 are reserved for future use.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with the BL being program-
mable, as shown in Figure 7 on page 18. BL determines the maximum number of
column locations that can be accessed for a given READ or WRITE command. BL of 1, 2,
4, or 8 locations are available for both the sequential and the interleaved burst types, and
a full-page burst is available for the sequential mode. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate arbitrary BLs.
Reserved states cannot be used because unknown operation or incompatibility with
future versions may result.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT48LC32M4A2TG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
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