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G
Core Logic Module
(Continued)
SL1 Sleep State (ACPI S1)
In this state the core processor is in 3V Suspend mode (all
its clocks are stopped, including the memory controller).
The SDRAM is placed in self-refresh mode. All other
SC1100 and system clocks are running. The frequency
multipliers (FMUL) and the PLLs are all running. All devices
are powered up (PWRCNT[2:1] and ONCTL# are all
asserted). See Section 5.2.9.5 "Usage Hints" on page 137.
No reset is performed, when exiting this state. The SC1100
keeps all context in this state. This state corresponds to
ACPI Sleep state S1.
SL2 Sleep State (ACPI S1)
In this state, all of the SC1100 clocks are stopped including
the FMULs and the PLLs, but not the 32 KHz oscillator.
Selected clocks from the FMULs and PLLs can be stopped.
The SDRAM is placed in self-refresh mode. The
PWRCNT1 pin is deasserted. The SC1100 itself is pow-
ered up. The system designer can decide which other sys-
tem devices to power off with the PWRCNT1 pin.
No reset is performed, when exiting this state. The SC1100
keeps all context in this state. This state corresponds to
ACPI sleep state S1, with lower power and longer wake
time than in SL1.
SL3 Sleep State (ACPI S3)
In this state, the SDRAM is placed in self-refresh mode,
and PWRCNT[2:1] are deasserted. PWRCNT[2:1] should
be used to power off most of the system (except for the
SDRAM). If the Save-to-RAM feature is used, external cir-
cuitry in the SDRAM interface is required to guarantee data
integrity. All SC1100 signals powered by V
SB
, V
SBL
or
V
BAT
are still functional to allow wakeup and to maintain
the real-time clock.
The power-up sequence is performed, when exiting this
state. This state corresponds to ACPI sleep state SL3.
SL4 and SL5 Sleep States (ACPI S4 and S5)
The SL4 and SL5 states are similar from the hardware per-
spective. In these states, the SC1100 deasserts
PWRCNT[2:1] and ONCTL#. PWRCNT[2:1] and ONCTL#
should be used to power off the system. All signals pow-
ered by V
SB
, V
SBL
or V
BAT
are still functional to allow
wakeup and to keep the real-time clock.
The power-up sequence is performed when exiting this
state. This state corresponds to ACPI Sleep states SL4
and SL5.
Table 5-5. Wakeup Events Capability
Event
S0/C1
S0/C3
SL1
SL2
SL3
SL4, SL5
Enabled Interrupts
Yes
Yes
Yes
-
-
-
SMI according to Table 5-8
Yes
Yes
Yes
-
-
-
SCI according to Table 5-8
Yes
Yes
Yes
-
-
-
GPIO[47:32], GPIO[15:0]
Yes
Yes
Yes
-
-
-
Power Button
Yes
Yes
Yes
Yes
Yes
Yes
Power Button Override
Yes
Yes
Yes
Yes
Yes
Yes
Bus Master Request
Yes
1
Yes
Yes
-
-
-
Thermal Monitoring
Yes
Yes
Yes
Yes
Yes
Yes
USB
Yes
Yes
Yes
Yes
-
-
IRRX1 (Infrared)
Yes
Yes
Yes
Yes
-
-
GPWIO[2:0]
Yes
Yes
Yes
Yes
Yes
Yes
RI# (UART)
Yes
Yes
Yes
Yes
-
-
RTC
Yes
Yes
Yes
Yes
Yes
Yes
1.
Temporarily exits state.