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| 型號(hào)： | SC1100 |
| 廠(chǎng)商： | National Semiconductor Corporation |
| 英文描述： | Geode⑩ Information Appliance On a Chip |
| 中文描述： | Geode⑩信息家電在一個(gè)芯片 |
| 文件頁(yè)數(shù)： | 137/348頁(yè) |
| 文件大?。?/td> | 2063K |
| 代理商： | SC1100 |
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Revision 1.1
137
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G
Core Logic Module
(Continued)
Power Button
The power button (PWRBTN#, ball AF15) input provides
two events: a wake request, and a sleep request. For both
these events, the PWRBTN# signal is debounced (i.e., the
signal state is transferred only after 14 to 16 msec without
transitions, to ensure that the signal is no longer bouncing).
ACPI is non-functional when the power-up sequence does
not include using the power button. If ACPI functionality is
desired, the power button must be toggled. This can be
done externally or internally. GPIO63 is internally con-
nected to PWRBTN#. To toggle the power button with soft-
ware, GPIO63 must be programmed as an output using the
normal GPIO programming protocol (see Section 5.4.1.1
"GPIO Support Registers" on page 196). GPIO63 must be
pulsed low for at least 16 msec and not more than 4 sec.
Asserting POR# has no effect on ACPI. If POR# is
asserted and ACPI was active prior to POR#, then ACPI
will remain active after POR#. Therefore, BIOS must
ensure that ACPI is inactive before GPIO63 is pulsed low.
Power Button Wake Event
- Detection of a high-to-low
transition on the debounced PWRBTN# input signal when
in SL1 to SL5 Sleep states. The system is considered in
the Sleep state, only after it actually transitioned into the
state and not only according to the SLP_TYP field.
In reaction to this event, the PWRBTN_STS bit
(F1BAR1+I/O Offset 08h[8]) is set to 1 and a wakeup event
or an interrupt is generated (note that this is regardless of
the PWRBTN_EN bit, F1BAR1+I/O Offset 0Ah[8]).
Power Button Sleep Event
- Detection of a high-to-low
transition on the debounced PWRBTN# input signal, when
in the Working state (S0).
In reaction to this event, the PWRBTN_STS bit is set to 1.
When both the PWRBTN_STS bit and the
PWRBTN_EN bit are set to 1, an SCI interrupt is gener-
ated.
When SCI_EN bit is 0, ONCTL# and PWRCNT[2:1] are
deasserted immediately regardless of the PWRBTN_EN
bit.
Power Button Override
When PWRBTN# is 0 for more than four seconds, ONCTL#
and PWRCNT[2:1] are deasserted (i.e., the system transi-
tions to the SL5 state, "Soft Off"). This power management
event is called the power button override event.
In reaction to this event, the PWRBTN_STS bit is cleared
to 0 and the PWRBTNOR_STS bit (F1BAR1+I/O Offset
08h[11]) is set to 1.
Thermal Monitoring
The thermal monitoring event (THRM#, ball AE15) enables
control of ACPI-OS Control.
When the THRM# signal transitions from high-to-low, the
THRM_STS bit (F1BAR1+I/O Offset 10h[5]) is set to 1. If
the THRM_EN bit (F1BAR1+I/O Offset 12h[5]) is also set
to 1, an interrupt is generated.
IRRX1, RI#
See Section 4.4.1 "SIO Control and Configuration Regis-
ters" on page 73 for control and operation.
5.2.9.5
Usage Hints
During initialization, the BIOS should:
— Clear the SUSP_HLT bit in CCR2 (GX1 module,
Index C2h[3]) to 0. This is needed for compliance
with C0 definition of ACPI, when the Halt instruction
(HLT) is executed.
— Disable the SUSP_3V option in C3 power state (F0
Index 60h[2]).
— Disable the SUSP_3V option in SL1 sleep state (F0
Index 60h[1]).
SMM code should clear the CLK_STP bit in the PM
Clock Stop Control register (GX_BASE+Memory Offset
8500h[0]) to 0 when entering C3 state.
SMM code should correctly set the CLK_STP bit in the
PM Clock Stop Control register (GX_BASE+Memory
Offset 8500h[0]) when entering the SL1, SL2, and SL3
states.
5.2.10 Power Management Programming
The power management resources provided by a com-
bined GX1 module and Core Logic module based system
supports a high efficiency power management implementa-
tion. The following explanations pertain to a full-featured
“notebook” power management system. The extent to
which these resources are employed depends on the appli-
cation and on the discretion of the system designer.
Power management resources can be grouped according
to the function they enable or support. The major functions
are as follows:
APM Support
CPU Power Management
— Suspend Modulation
— 3V Suspend
— Save-to-Disk
Peripheral Power Management
— Device Idle Timers and Traps
— General Purpose Timers
— ACPI Timer Register
— Power Management SMI Status Reporting Registers
Included in the following subsections are details regarding
the registers used for configuring power management fea-
tures. The majority of these registers are directly accessed
through the PCI configuration register space designated as
Function 0 (F0). However, included in the discussions are
references to F1BARx+I/O Offset xxh. This refers to regis-
ters accessed through base address registers in Function 1
(F1) at Index 10h (F1BAR0) and Index 40h (F1BAR1).
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