Revision 1.1
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G
SuperI/O Module
(Continued)
Index 0Dh
Width: Byte
RTC Control Register D - CRD (RO)
Reset Type: V
PP
PUR
7
Valid RAM and Time.
This bit senses the voltage that feeds the RTC (VSB or VBAT) and indicates whether or not it was too
low since the last time this bit was read. If it was too low, the RTC contents (time/calendar registers and CMOS RAM) are
not valid.
0: The voltage that feeds the RTC was too low.
1: RTC contents (time/calendar registers and CMOS RAM) are valid.
Reserved.
6:0
Index Programmable
Width: Byte
Date of Month Alarm Register - DOMA (R/W)
Reset Type: V
PP
PUR
7:0
Date of Month Alarm Data
. Values may be 01 to 31 in BCD format or 01 to 1F in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)
Index Programmable
Width: Byte
Month Alarm Register - MONA (R/W)
Reset Type: V
PP
PUR
7:0
Month Alarm Data.
Values may be 01 to 12 in BCD format or 01 to 0C in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)
Index Programmable
Width: Byte
Century Register - CEN (R/W)
Reset Type: V
PP
PUR
7:0
Century Data.
Values may be 00 to 99 in BCD format or 00 to 63 in Binary format.
Table 4-18. RTC Registers (Continued)
Bit
Description
Table 4-19. Divider Chain Control / Test Selection
DV2
DV1
DV0
Configuration
CRA6
CRA5
CRA4
0
0
X
Oscillator Disabled
0
1
0
Normal Operation
0
1
1
Test
1
0
X
1
1
X
Divider Chain Reset
Table 4-20. Periodic Interrupt Rate Encoding
Rate Select
3 2 1 0
Periodic Interrupt
Rate (msec)
Divider
Chain Output
0 0 0 0
No interrupts
0 0 0 1
3.906250
7
0 0 1 0
7.812500
8
0 0 1 1
0.122070
2
0 1 0 0
0.244141
3
0 1 0 1
0.488281
4
0 1 1 0
0.976562
5
0 1 1 1
1.953125
6
1 0 0 0
3.906250
7
1 0 0 1
7.812500
8
1 0 1 0
15.625000
9
1 0 1 1
31.250000
10
1 1 0 0
62.500000
11
1 1 0 1
125.000000
12
1 1 1 0
250.000000
13
1 1 1 1
500.000000
14