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156
Revision 1.1
G
Core Logic Module
(Continued)
Table 5-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
F1 Index
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-32)
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh
0Fh
10h-13h
16
16
16
16
8
24
8
8
8
8
32
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F1BAR0) — Sets the base address for
the I/O mapped SMI Status Registers (summarized in Table 5-18).
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
Base Address Register 1 (F1BAR1) — Sets the base address for
the I/O mapped ACPI Support Registers (summarized in Table 5-
19)
Reserved
100Bh
0511h
0000h
0280h
00h
068000h
00h
00h
00h
00h
00000001h
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14h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h-43h
--
16
16
--
32
--
00h
100Bh
0501h
00h
00000001h
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RO
RO
--
R/W
44h-FFh
--
--
00h
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Table 5-18. F1BAR0: SMI Status Registers Summary
F1BAR0+
I/O Offset
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-33)
00h-01h
02h-03h
04h-05h
16
16
16
RO
Top Level PME/SMI Status Mirror Register
Top Level PME/SMI Status Register
Second Level General Traps & Timers PME/SMI Status Mirror
Register
Second Level General Traps & Timers PME/SMI Status Register
SMI Speedup Disable Register
0000h
0000h
0000h
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RO/RC
RO
06h-07h
08h-09h
16
16
RC
0000h
0000h
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Read to
Enable
--
RO
RO
RC
R/W
--
--
0Ah-1Bh
1Ch-1Fh
20h-21h
22h-23h
24h-27h
28h-4Fh
50h-FFh
--
32
16
16
32
--
--
Reserved
ACPI Timer Register
Second Level ACPI PME/SMI Status Mirror Register
Second Level ACPI PME/SMI Status Register
External SMI Register
Not Used
The I/O mapped registers located here (F1BAR0+I/O Offset 50h-FFh) are also accessible at F0
Index 50h-FFh. The preferred method is to program these registers through the F0 register space.
00h
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xxxxxxxxh
0000h
0000h
00000000h
00h