Revision 1.1
257
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G
Core Logic Module
(Continued)
Offset 2Ch-2Fh
HcBulkCurrentED Register (R/W)
Reset Value = 00000000h
31:4
BulkCurrentED.
Pointer to the current Bulk List ED.
3:0
Reserved.
Read/Write 0s.
Offset 30h-33h
HcDoneHead Register (R/W)
Reset Value = 00000000h
31:4
DoneHead.
Pointer to the current Done List Head ED.
3:0
Reserved.
Read/Write 0s.
Offset 34h-37h
HcFmInterval Register (R/W)
Reset Value = 00002EDFh
31
FrameIntervalToggle (Read Only).
This bit is toggled by HCD when it loads a new value into FrameInterval.
30:16
FSLargestDataPacket (Read Only).
This field specifies a value which is loaded into the Largest Data Packet Counter at
the beginning of each frame.
15:14
Reserved.
Read/Write 0s.
13:0
FrameInterval.
This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999
is stored here.
Offset 38h-3Bh
HcFrameRemaining Register (RO)
Reset Value = 00000000h
31
FrameRemainingToggle (Read Only).
Loaded with FrameIntervalToggle when FrameRemaining is loaded.
30:14
Reserved.
Read 0s.
13:0
FrameRemaining (Read Only).
When the HC is in the UsbOperational state, this 14-bit field decrements each 12 MHz
clock period. When the count reaches 0, (end of frame) the counter reloads with FrameInterval. In addition, the counter
loads when the HC transitions into UsbOperational.
Offset 3Ch-3Fh
HcFmNumber Register (RO)
Reset Value = 00000000h
31:16
Reserved.
Read 0s.
15:0
FrameNumber (Read Only).
This 16-bit incrementing counter field is incremented coincident with the loading of FrameR-
emaining. The count rolls over from FFFFh to 0h.
Offset 40h-43h
HcPeriodicStart Register (R/W)
Reset Value = 00000000h
31:14
Reserved.
Read/Write 0s.
13:0
PeriodicStart.
This field contains a value used by the List Processor to determine where in a frame the Periodic List pro-
cessing must begin.
Offset 44h-47h
HcLSThreshold Register (R/W)
Reset Value = 00000628h
31:12
Reserved.
Read/Write 0s.
11:0
LSThreshold.
This field contains a value used by the Frame Management block to determine whether or not a low speed
transaction can be started in the current frame.
Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description