Revision 1.1
153
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G
Core Logic Module
(Continued)
70h-71h
72h
73h
74h-75h
76h
77h
78h-7Bh
7Ch-7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh-92h
93h
94h-95h
96h
97h
98h-99h
9Ah-9Bh
9Ch-9Dh
9Eh-9Fh
A0h-A1h
A2h-A3h
A4h-A5h
AAh-ABh
ACh-ADh
AEh
AFh
B0h-B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh-BFh
16
8
8
16
8
--
32
32
8
8
8
8
8
8
8
8
8
8
8
8
8
--
8
16
8
--
16
16
16
16
16
16
16
--
16
8
8
--
8
8
8
8
8
8
8
8
8
--
R/W
R/W
---
R/W
R/W
--
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
--
R/W
R/W
R/W
--
R/W
R/W
R/W
R/W
R/W
R/W
R/W
--
R/W
WO
WO
--
RO
RO
RO
RO
RO
RO
RO
RO
R/W
--
IOCS1# Base Address Register
IOCS1# Control Register
Reserved
IOCS0 Base Address Register
IOCS0 Control Register
Reserved
DOCCS Base Address Register
DOCCS Control Register
Power Management Enable Register 1
Power Management Enable Register 2
Power Management Enable Register 3
Power Management Enable Register 4
Second Level PME/SMI Status Mirror Register 1
Second Level PME/SMI Status Mirror Register 2
Second Level PME/SMI Status Mirror Register 3
Second Level PME/SMI Status Mirror Register 4
General Purpose Timer 1 Count Register
General Purpose Timer 1 Control Register
General Purpose Timer 2 Count Register
General Purpose Timer 2 Control Register
IRQ Speedup Timer Count Register
Reserved
Miscellaneous Device Control Register
Suspend Modulation Register
Suspend Configuration Register
Reserved
Hard Disk Idle Timer Count Register — Primary Channel
Floppy Disk Idle Timer Count Register
Parallel / Serial Idle Timer Count Register
Keyboard / Mouse Idle Timer Count Register
User Defined Device 1 Idle Timer Count Register
User Defined Device 2 Idle Timer Count Register
User Defined Device 3 Idle Timer Count Register
Reserved
Hard Disk Idle Timer Count Register — Secondary Channel
CPU Suspend Command Register
Suspend Notebook Command Register
Reserved
Floppy Port 3F2h Shadow Register
Floppy Port 3F7h Shadow Register
Floppy Port 1F2h Shadow Register
Floppy Port 1F7h Shadow Register
DMA Shadow Register
PIC Shadow Register
PIT Shadow Register
RTC Index Shadow Register
Clock Stop Control Register
Reserved
0000h
00h
00h
0000h
00h
00h
00000000h
00000000h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0000h
00h
00h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00h
0000h
00h
00h
00h
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
00h
00h
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Table 5-14. F0: PCI Header and Bridge Configuration Registers
for GPIO and LPC Support Summary (Continued)
F0 Index
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-29)