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Signal Definitions
(Continued)
SMI_O
AC12
O
System Management Interrupt.
This
is the input to the GX1 core. When
enabled, this signal provides for moni-
toring of the internal GX1 core SMI#
signal for debug purposes. To enable,
pull up FPCI_MON (ball AB25).
GPIO8+CTS#+IDE_DREQ1
2.4.14 JTAG Interface Signals
Signal Name
Ball No.
Type
Description
Mux
TCK
AE20
I
JTAG Test Clock.
This signal has an internal weak pull-
up resistor.
---
TDI
AF20
I
JTAG Test Data Input.
This signal has an internal weak
pull-up resistor.
---
TDO
AD20
O
JTAG Test Data Output
---
TMS
AF21
I
JTAG Test Mode Select.
This signal has an internal
weak pull-up resistor.
---
TRST#
AC20
I
JTAG Test Reset.
This signal has an internal weak pull-
up resistor.
For normal JTAG operation, this signal should be active
at power-up.
If the JTAG interface is not being used, this signal can be
tied low.
---
2.4.15 Test and Measurement Interface Signals
Signal Name
Ball No.
Type
Description
Mux
FMUL3B
AD10
I/O
FMUL3 Bypass.
This signal is used for internal testing
only. For normal operation, leave this signal uncon-
nected.
TEST1
GXCLK
C20
O
GX Clock.
This signal is used for internal testing only.
For normal operation, program as IRTX or leave uncon-
nected.
IRTX+TEST3
PLL5B
AC11
I/O
PLL5 Bypass.
This signal is for internal testing only.
For normal operation, leave this signal unconnected.
TEST2
TEST3
C20
O
Internal Test Signals.
These signals are used for
internal testing only. For normal operation, leave these
signals unconnected unless programmed as one of
their muxed options.
GXCLK+IRTX
TEST2
AC11
O
PLL5B
TEST1
AD10
O
FMUL3B
TEST0
AA24
O
GPIO41+
F_C/BE0#
SDTEST5
B20
O
Memory Internal Test Signals.
These signals are
used for internal testing only. For normal operation,
leave SDTEST[4:1] unconnected and program
SDTEST5 to function as GPIO40.
GPIO40+F_AD6
SDTEST4
E3
O
---
SDTEST3
D5
O
---
SDTEST2
A18
O
---
SDTEST1
D1
O
---
SDTEST0
A20
O
---
2.4.13 Debug Monitoring Interface Signals (Continued)
Signal Name
Ball No.
Type
Description
Mux