Revision 1.1
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G
SuperI/O Module
(Continued)
4.4.2.5
Table 4-13 lists the configuration registers which affect the
Serial Port (SP). Only the last register (F0h) is described
LDN 08h - SP Configuration
here (Table 4-14). See Table 4-3 "Standard Configuration
Registers" on page 71 for descriptions of the others.
Table 4-13. SP Relevant Registers
Index
Type
Configuration Register or Action
Reset
Value
30h
R/W
Activate.
See also bit 0 of the SIOCF1 register.
00h
60h
R/W
Base Address MSB register.
Bits [7:3] (for A[15:11]) are RO, 00000b.
02h
61h
R/W
Base Address LSB register
. Bits [2:0] (for A[2:0]) are RO, 000b.
F8h
70h
R/W
Interrupt Number.
03h
71h
R/W
Interrupt Type.
Bit 1 is R/W; other bits are RO.
03h
74h
RO
Report no DMA assignment
.
04h
75h
RO
Report no DMA assignment.
04h
F0h
R/W
Serial Port Configuration register.
(See Table 4-14.)
02h
Table 4-14. SP Configuration Register
Bit
Description
Index F0h
Serial Port Configuration Register (R/W)
Reset Value: 02h
7
Bank Select Enable
. Enables bank switching.
0: Disabled. (Default)
1: Enabled.
Reserved.
Busy Indicator. (RO)
This bit can be used by power management software to decide when to power-down the logical
device.
0: No transfer in progress. (Default)
1: Transfer in progress.
Power Mode Control.
When the logical device is active in:
0: Low power mode - Serial Port clock disabled. The output signals are set to their default states. Registers are maintained.
(Unlike Active bit in Index 30h that also prevents access to Serial Port registers.)
1: Normal power mode - Serial Port clock enabled. Serial Port is functional when the respective logical device is active.
(Default)
TRI-STATE Control
. This bit controls the TRI-STATE status of the device output pins when it is inactive (disabled).
0: Disabled. (Default)
1: Enabled when device inactive.
6:3
2
1
0