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Revision 1.1
G
Core Logic Module
(Continued)
0
Hard Disk Idle Timer SMI Status.
Indicates whether or not an SMI was caused by expiration of Hard Disk Idle Timer Count
Register (F0 Index 98h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[0] = 1.
Index F6h
The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].
Reading this register clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F0 Index 86h. If the value of the register must be read without clearing the SMI
source (and consequently deasserting SMI), F0 Index 86h can be read instead.
Second Level PME/SMI Status Register 3 (RC)
Reset Value: 00h
7
6
5
Reserved.
Reads as 0.
Reserved. (Read Only)
Secondary Hard Disk Access Trap SMI Status.
Indicates whether or not an SMI was caused by a trapped I/O access to
the secondary hard disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[6] = 1.
Secondary Hard Disk Idle Timer SMI Status.
Indicates whether or not an SMI was caused by expiration of Secondary
Hard Disk Idle Timer Count register (F0 Index ACh).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[7] = 1.
Keyboard/Mouse Access Trap SMI Status.
Indicates whether or not an SMI was caused by a trapped I/O access to the
keyboard or mouse.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[3] = 1.
Parallel/Serial Access Trap SMI Status.
Indicates whether or not an SMI was caused by a trapped I/O access to either the
serial or parallel ports.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[2] =1.
Floppy Disk Access Trap SMI Status.
Indicates whether or not an SMI was caused by a trapped I/O access to the floppy
disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[1] = 1.
Primary Hard Disk Access Trap SMI Status.
Indicates whether or not an SMI was caused by a trapped I/O access to the
primary hard disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[0] = 1.
4
3
2
1
0
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description