
Revision 1.1
63
www.national.com
G
General Configuration Block
(Continued)
3.5.6
Clock Registers
Table 3-8. Clock Generator Configuration
Bit
Description
Offset: 10h
Width: Byte
This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI clock
multiplied by this value.
Maximum Core Clock Multiplier Register - MCCM (RO)
Reset Value: Strapped Value
7:4
3:0
Reserved.
MCM (Maximum Clock Multiplier).
This 4-bit value is the maximum multiplier value allowed for the core clock generator. It
is derived from strap options CLKSEL[3:0] (balls AE22, AD22, AD25, D23).
Offset: 12h
Width: Byte
This register controls operation of the PLLs.
PLL Power Control Register - PPCR (R/W)
Reset Value: 2Fh
7
6
Reserved.
Write as read.
EXPCID (Disable External PCI Clock).
0: External PCI clock is enabled.
1: External PCI clock is disabled.
Reserved.
Must be written as 1.
Reserved.
Write as read.
PLL3SD (Shut Down PLL3).
AC97 codec clock.
0: PLL3 is enabled.
1: PLL3 is shutdown.
FM1SD (Shut Down PLL4).
0: PLL4 is enabled.
1: PLL4 is shutdown.
C48MD (Disable SuperI/O and USB Clock).
0: USB and SuperI/O clock is enabled.
1: USB and SuperI/O clock is disabled.
Reserved.
Write as read.
5
4
3
2
1
0
Offset: 18h
Width: DWORD
PLL3 Configuration Register - PLL3C (R/W)
Reset Value: E1040005h
31:24
MFFC (MFF Counter Value).
F
VCO
= OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz
Reserved.
Write as read.
MFBC (MFB Counter Value).
F
VCO
= OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz
Reserved.
Write as read.
Reserved.
Must be set to 0.
MOC (MO Counter Value).
F
VCO
= OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz
23:19
18:8
7
6
5:0