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參數(shù)資料
| 型號： | TFRA08C13 |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 10/188頁 |
| 文件大小： | 3047K |
| 代理商： | TFRA08C13 |
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Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
10
L Lucent Technologies Inc.
Feature Descriptions
T1/E1 Framer Feature Descriptions
I
Framing formats:
— Compliant with T1 standards ANSIT1.231 (1993),
AT&T TR54016, AT&T TR62411 (1998).
— Unframed, transparent transmission in T1 and E1
formats.
— DS1 extended superframe (ESF).
— DS1 superframe (SF): D4; SLC-96; T1DM DDS;
T1DM DDS with FDL access.
— DS1 independent transmit and receive framing
modes when using the ESF and D4 formats.
— Compliant with ITU CEPT framing recommenda-
tion:
1. G.704 and G.706 basic frame format.
2. G.704 Section 2.3.3.4 and G.706 Section 4.2:
CRC-4 multiframe search algorithm.
3. G.706 Annex B: CRC-4 multiframe search algo-
rithm with 400 ms timer for interworking of
CRC-4 and non-CRC-4 equipment.
4. G.706 Section 4.3.2 Note 2: monitoring of 915
CRC-4 checksum errors for loss of frame state.
I
Framer line codes:
— DS1: alternate mark inversion (AMI); binary eight
zero code suppression (B8ZS); per-channel zero
code suppression; decoding bipolar violation mon-
itor; monitoring of eight or fifteen bit intervals with-
out positive or negative pulses error indication.
— DS1 independent transmit and receive path line
code formats when using AMI/ZCS and B8ZS
coding.
— ITU-CEPT: AMI; high-density bipolar 3 (HDB3)
encoding and decoding bipolar violation monitor-
ing, monitoring of four bit intervals without positive
or negative pulses error indication.
— Single-rail option.
I
Signaling:
— DS1: extended superframe 2-state, 4-state, and
16-state per-channel robbed bit.
— DS1: D4 superframe 2-state and 4-state per-
channel robbed bit.
— DS1: SLC-96 superframe 2-state, 4-state, 9-state,
and 16-state per-channel robbed bit.
— DS1: channel-24 message-oriented signaling.
— ITU CEPT: channel associated signaling (CAS).
— Transparent (all data channels).
I
Alarm reporting, performance monitoring, and main-
tenance:
— ANSI T1.403-1995, AT&T TR 54016, and ITU
G.826 standard error checking.
— Error and status counters:
1. Bipolar violations.
2. Errored frame alignment signals.
3. Errored CRC checksum block.
4. CEPT: received E bit = 0.
5. Errored, severely errored, and unavailable
seconds.
— Selectable errored event monitoring for errored
and severely errored seconds processing with
programmable thresholds for errored and severely
errored second monitoring.
— CEPT: Selectable automatic transmission of E bit
to the line.
— CEPT: Sa6 coded remote end CRC-4 error E bit =
0 events.
— Programmable automatic and on-demand alarm
transmission:
1. Automatic transmission of remote frame alarm
to the line while in loss of frame alignment
state.
2. Automatic transmission of alarm indication
signal (AIS) to the system while in loss of frame
alignment state.
— Multiple loopback modes.
— Optional automatic line and payload loopback acti-
vate and deactivate modes.
— CEPT nailed-up connect loopback and CEPT
nailed-up broadcast transmission TS-X in TS-0
transmit mode.
— Selectable test patterns for line transmission.
— Detection of framed and unframed pseudorandom
and quasi-random test patterns.
— Programmable squelch and idle codes.
I
System interface:
— Autonomous transmit and receive system inter-
faces.
— Independent transmit and receive frame synchro-
nization input signals.
— Independent transmit and receive system interface
clock.
— 2.048 Mbits/s, 2.048 MHz concentration highway
interface (CHI) default mode.
— Optional 4.096 Mbits/s and 8.192 Mbits/s data
rates.
— Optional 4.096 MHz and 8.192 MHz frequency
system clock.
— Programmable clock edge for latching frame syn-
chronization signals.
— Programmable clock edge for latching transmit
and receive data.
— Programmable bit and byte offset.
— Programmable CHI master mode for the genera-
tion of the transmit CHI FS from internal logic with
timing derived from the receive line clock signal.
I
Digital phase comparator for clock generation in the
receive and transmit paths.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TFRA08C13-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:TFRA08C13 OCTAL T1/E1 Framer |
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| TFRA84J13 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| TFRA84J131BL-3-DB | 制造商:LSI Corporation 功能描述:Framer DS0/DS1/DS2/DS3/E1/E2/E3 1.5V/3.3V 909-Pin BGA |
| TFRA84J13DS0 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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