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參數(shù)資料
| 型號(hào)： | TFRA08C13 |
| 廠商： | Lineage Power |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 96/188頁(yè) |
| 文件大?。?/td> | 3047K |
| 代理商： | TFRA08C13 |
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96
LLucent Technologies Inc.
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link
(continued)
5-4563(F)r.1
Figure 35. Remote Loopback Mode
XMIT HDLC FDL BLOCK
XMIT HDLC
FDL XMIT
INTERFACE
XMIT FIFO
RCVR FIFO
RCVR HDLC
FDL RCVR
INTERFACE
TFDL
TFDLCK
RFDLCK
RFDL
RCVR HDLC FDL BLOCK
Phase-Lock Loop Circuit
The TFRA08C13 allows for independent transmit path
and receive path clocking. The device provides outputs
to control variable clock oscillators on both the transmit
and receive paths. As such, the system may have both
the transmit and receive paths phase-locked to two
autonomous clock sources.
The block diagram of the TFRA08C13 phase detector
circuitry is shown in Figure 36. The TFRA08C13 uses
elastic store buffers (two frames) to accommodate the
transfer of data from the system interface clock rate of
2.048 Mbits/s to the line interface clock rate of either
1.544 Mbits/s or 2.048 Mbits/s. The transmit line side of
the TFRA08C13 does not have any mechanism to
monitor data overruns or underruns (slips) in its elastic
store buffer. This interface relies on the requirement
that the PLLCK clock signal (variable) is phase-locked
to the CHICK clock signal (reference). When this
requirement is not met, uncontrolled slips may occur in
the transmit elastic store buffer that would result in cor-
rupting data and no indication will be given. Typically, a
variable clock oscillator (VCXO) is used to drive the
PLLCK signal. The TFRA08C13 provides a phase error
signal (PLLCK-EPLL) that can be used to control the
VCXO PLLCK. The PLLCK-EPLL signal is generated
by monitoring the divided-down PLLCK (DIV-PLLCK)
and CHICK (DIV-CHICK) signals. The DIV-CHICK sig-
nal is used as the reference to determine the phase dif-
ference between DIV-CHICK and DIV-PLLCK. While
DIV-CHICK and DIVPLLCK are phase-locked, the
PLLCK-EPLL signal is in a high-impedance state. A
phase difference between DIV-CHICK and DIV-PLLCK
drives PLLCK-EPLL to either 3.3 V or 0 V. An appropri-
ate loop filter, for example, an RC circuit with R = 1 k
and C = 0.1 μF, is used to filter these PLLCK-EPLL
pulses to control the VCXO.
The system can force CHICK to be phase-locked to
RLCK by using RLCK as a reference signal to control a
VCXO that is sourcing the CHICK signal. The
TFRA08C13 uses the receive line signal (RLCK) as the
reference and the CHICK signal as the variable signal.
The TFRA08C13 provides a phase error signal
(CHICK-EPLL) that can be used to control the VCXO
generating CHICK. The CHICK-EPLL signal is gener-
ated by monitoring the divided-down CHICK signal
(DIV-CHICK) and RLCK (DIV-RLCK) signals. The DIV-
RLCK signal is used as the reference to determine the
phase difference between DIV-CHICK and DIV-RLCK.
While DIV-RLCK and DIV-CHICK are phase-locked, the
CHICK-EPLL signal is in a high-impedance state. A
phase difference between DIV-RLCK and DIV-CHICK
drives CHICK-EPLL to either 3.3 V or 0 V. An appropri-
ate loop filter, for example, an RC circuit with R = 1 k
and C = 0.1 μF, is used to filter these CHICK-EPLL
pulses to control the VCXO. In this mode, the
TFRA08C13 can be programmed to act as a master
timing source and is capable of generating the system
frame synchronization signal through the CHIFS pin
and setting FRM_PR45 bit 4 to 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TFRA08C13-DB | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:TFRA08C13 OCTAL T1/E1 Framer |
| TFRA28J133BAL-1 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecomm/Datacomm |
| TFRA84J13 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| TFRA84J131BL-3-DB | 制造商:LSI Corporation 功能描述:Framer DS0/DS1/DS2/DS3/E1/E2/E3 1.5V/3.3V 909-Pin BGA |
| TFRA84J13DS0 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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