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參數(shù)資料
| 型號(hào)： | TFRA08C13 |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 19/188頁(yè) |
| 文件大?。?/td> | 3047K |
| 代理商： | TFRA08C13 |
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Lucent Technologies Inc.
19
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Pins
Symbol
Type
*
Description
AE9
SECOND
O
Second Pulse.
A one second timer with an active-high pulse. The
duration of the pulse is one RLCK cycle. Framer_1’s receive line clock
signal (RLCK1) is the default clock source for the internal second pulse
timer. The internal second pulse is retimed in the individual framer sec-
tions with their corresponding receive line clock signal RLCK. When
LORLCK_(N) is active, then Framer_(N + 1)’s receive line clock signal
is used as the clock signal source for the internal second pulse timer.
The second pulse is used for performance monitoring.
CHI Clock.
2.048 MHz,
4.096 MHz, or 8.192 MHz.
CHI Frame Sync.
CHI 8 kHz input frame synchronization pulse. Pulse
width must be a minimum of one clock period of CHICK and a maxi-
mum of a 50% duty cycle square wave.
Error Phase-Lock Loop Signal.
The error signal proportional to the
phase difference between DIV-CHICK and DIV-RLCK as detected from
the internal PLL circuitry (see Table 66. Global Control Register
(GREG8) (008)
Divided-Down PLLCK Clock.
32 kHz or 8 kHz clock signal derived
from the PLLCK input signal (see Table 150. CHI Common Control
Register (FRM_PR45) (Y8D)).
Error Phase-Lock Loop Signal.
The error signal proportional to the
phase difference between DIV-PLLCK and DIV-CHICK as detected by
the internal PLL circuitry (refer to the Phase-Lock Loop section).
Divided-Down Receive Line Clock.
8 kHz clock signal derived from
the recovered receive line interface unit clock or the RLCK input signal.
The choice of which receive framer clock to use is defined in Table 66.
Global Control Register (GREG8) (008).
Divided-Down CHI Clock.
8 kHz clock signal derived from the transmit
CHI CLOCK input signal (see Table 66. Global Control Register
(GREG8) (008)).
DS1/CEPT.
Strap to V
DD
to enable DS1 operation in the framer unit.
Strap to V
SS
to enable CEPT operation in the framer unit.
D18
CHICK
I
A19
CHIFS
I
H24
CHICK-EPLL
O
G25
DIV-PLLCK
O
G26
PLLCK-EPLL
O
H23
DIV-RLCK
O
H26, J24
DIV-CHICK
O
J4
V1
AE5
AD19
AC20
T25
F26
B12
DS1/CEPT[1]
DS1/CEPT[2]
DS1/CEPT[3]
DS1/CEPT[4]
DS1/CEPT[5]
DS1/CEPT[6]
DS1/CEPT[7]
DS1/CEPT[8]
I
u
* I
u
indicates an internal pull-up, I
d
indicates an internal pull-down.
After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
Asserting this pin low will initially force RDY to a low state.
Pin Information
(continued)
Table 2. Pin Descriptions
(continued)
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相關(guān)代理商/技術(shù)參數(shù) |
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| TFRA08C13-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:TFRA08C13 OCTAL T1/E1 Framer |
| TFRA28J133BAL-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| TFRA84J13 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| TFRA84J131BL-3-DB | 制造商:LSI Corporation 功能描述:Framer DS0/DS1/DS2/DS3/E1/E2/E3 1.5V/3.3V 909-Pin BGA |
| TFRA84J13DS0 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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