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參數(shù)資料
| 型號(hào)： | TFRA08C13 |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 12/188頁(yè) |
| 文件大?。?/td> | 3047K |
| 代理商： | TFRA08C13 |
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Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
12
L Lucent Technologies Inc.
Functional Description
(continued)
The Lucent Technologies Microelectronics Group
TFRA08C13 OCTAL T1/E1 Framer provides eight com-
plete T1/E1 interfaces each consisting of a fully inte-
grated, full-featured, primary rate framer with an HDLC
formatter for facility data link access. The TFRA08C13
provides glueless interconnection from a T1 or E1 ana-
log line interface to devices interfacing to its CHI; for
example, the Lucent T7270 Time-Slot Interchanger or
T7115A Synchronous Protocol Data Formatter.
The line codes supported in the framer unit include
AMI, T1 B8ZS, per-channel T1 zero code suppression,
and ITU-CEPT HDB3.
The framer supports DS1 superframe (D4, T1DM,
SLC-96) and extended superframe (ESF) formats. The
framer also supports, ITU-CEPT-E1 basic frame,
ITU-CEPT-E1 time slot 0 multiframe, and time slot 16
multiframe formats.
The receive framer monitors the following alarms: loss
of receive clock, loss of frame, alarm indication signal
(AIS), remote frame alarms, and remote multiframe
alarms. These alarms are detected as defined by the
appropriate ANSI AT&T, and ITU standards. It is rec-
ommended that the LIU/Framer interface be placed in
dual rail mode, which allows the framers error/event
detector to detect and report code and BPV errors.
Performance monitoring as specified by AT&T, ANSI
and ITU is provided through counters monitoring bipo-
lar violation, frame bit errors, CRC errors, errored
events, errored seconds, bursty errored seconds,
severely errored seconds, and unavailable seconds.
In-band loopback activation and deactivation codes
can be transmitted to the line via the payload or the
facility data link. In-band loopback activation and deac-
tivation codes in the payload or the facility data link are
detected.
System, payload, and line loopbacks are programma-
ble.
The default system interface is a 2.048 Mbits/s data
and 2.048 MHz clock CHI serial bus. This CHI interface
consists of independent transmit and receive paths.
The CHI interface can be reconfigured into several
modes: a 2.048 Mbits/s data interface and 4.096 MHz
clock interface, a 4.096 Mbits/s data interface and
4.096 MHz clock interface, a 4.096 Mbits/s data inter-
face and 8.192 MHz clock interface, a 8.192 Mbits/s
data interface and 8.192 MHz clock interface, and
8.192 Mbits/s data interface.
The signaling formats supported are T1 per-channel
robbed-bit signaling (RBS), channel-24 message-ori-
ented signaling (MOS), and ITU-CEPT-E1 channel-
associated signaling (CAS). In the T1, RBS mode voice
and data channels are programmable. The entire pay-
load can be forced into a data-only (no signaling chan-
nels) mode, i.e., transparent mode by programming
one control bit. Signaling access can be through the
on-chip signaling registers or the system CHI port in
the associated signaling mode. Data and its associated
signaling information can be accessed through the CHI
in either DS1 or CEPT-E1 modes.
Extraction and insertion of the facility data link in ESF,
T1DM, SLC-96, or CEPT-E1
modes are provided
through a four-port serial interface or through a micro-
processor-accessed, 64-byte FIFO either with HDLC
formatting or transparently. In SLC-96 or CEPT-E1
frame formats, a facility data link (FDL) stack (registers
in the framer section) is provided for FDL access. The
bit-oriented ESF data-link messages defined in ANSI
T1.403-1995 are monitored by the receive framer’s
facility data link unit. The transmit framer’s facility data
link unit overrides the XFDL-FIFO for the transmission
of the bit-oriented ESF data-link messages defined in
ANSIT1.403-1995.
The receive framer includes a two-frame (64-bytes)
elastic store buffer for jitter attenuation that performs
controlled slips and provides an indication of slip direc-
tion. This buffer can be programmed to operate as a
function of the receive line clock and can be reduced to
one-frame (32-bytes) in length.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TFRA08C13-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:TFRA08C13 OCTAL T1/E1 Framer |
| TFRA28J133BAL-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| TFRA84J13 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| TFRA84J131BL-3-DB | 制造商:LSI Corporation 功能描述:Framer DS0/DS1/DS2/DS3/E1/E2/E3 1.5V/3.3V 909-Pin BGA |
| TFRA84J13DS0 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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