參數(shù)資料
型號: TFRA08C13
廠商: Lineage Power
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 135/188頁
文件大?。?/td> 3047K
代理商: TFRA08C13
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Lucent Technologies Inc.
135
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture
(continued)
Bit 0—bit 4 in this register are set high when the receive framer comes out of the unavailable state, while
bit 4—bit 7 report detection of the receive test patterns. Bits 4 and 5 are cleared only after register FRM_PR70
bit 2 is set to 0.
Table 76. Facility Event Register (FRM_SR7) (Y07)
* It is possible for one of these bits to be set to 1, if the received line data is all zeros.
Bipolar Violation Counter Register (FRM_SR8—FRM_SR9)
This register contains the 16-bit count of received bipolar violations, line code violations, or excessive zeros.
Table 77. Bipolar Violation Counter Registers (FRM_SR8—FRM_SR9) (Y08—Y09)
Frame Bit Errored Counter Register (FRM_SR10—FRM_SR11)
This register contains the 16-bit count of framing bit errors. Framing bit errors are not counted during loss of frame
alignment.
Table 78. Framing Bit Error Counter Registers (FRM_SR10—FRM_SR11) (Y0A—Y0B)
Bit
0
Symbol
OUAS
Description
Out of Unavailable State.
A 1 indicates the receive framer detected ten consecutive
seconds that were not severely errored while in the unavailable state at the ET.
Out of Unavailable State at the ET-RE.
A 1 indicates the receive framer detected ten
consecutive seconds that were not severely errored while in the unavailable state at the
ET-RE.
Out of Unavailable State at the NT1.
A 1 indicates the receive framer detected ten con-
secutive seconds that were not severely errored while in the unavailable state at the NT.
Out of Unavailable State NT1-RE.
A 1 indicates the receive framer detected ten con-
secutive seconds that were not severely errored while in the unavailable state at the NT-
RE.
Test Pattern Detected.
A 1 indicates the pattern detector has locked onto the pattern
specified by the PTRN configuration bits defined in register FRM_PR70.
Test Pattern Bit Error.
A 1 indicates the pattern detector has found one or more single
bit errors in the pattern that it is currently locked onto.
Receiving Pseudorandom Pattern.
A 1 indicates the receive framer pattern monitor
circuit is currently detecting the 2
15
– 1 pseudorandom pattern*.
Receiving Quasi-Random Pattern.
A 1 indicates the receive framer pattern monitor cir-
cuit is currently detecting the 2
20
– 1 quasi-random pattern*.
1
EROUAS
2
NT1OUAS
3
NROUAS
4
DETECT
5
PTRNBER
6
RPSUEDO
7
RQUASI
Register
FRM_SR8
FRM_SR9
Byte
MSB
LSB
Bit
7—0
7—0
Symbol
BPV15—BPV8
BPV7—BPV0
Description
BPVs Counter.
BPVs Counter.
Register
FRM_SR10
FRM_SR11
Byte
MSB
LSB
Bit
7—0
7—0
Symbol
FBE15—FBE8
FBE7—FBE0
Description
Frame Bit èrrored Counter.
Frame Bit Errored Counter.
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