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參數(shù)資料
| 型號： | TFRA08C13 |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 127/188頁 |
| 文件大小： | 3047K |
| 代理商： | TFRA08C13 |
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Lucent Technologies Inc.
127
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Global Register Structure
(continued)
Global PLLCK Control Register (GREG9)
This register selectively enables/disables an individual transmit framer’s internal clock synthesizer. setting all bits to
0 (the default condition) disables all transmit framer clock synthesizers, and allows an external source of PLLCK to
drive the transmit framers.
Table 67. Global PLLCK Control Register (GREG9) (009)
Bit
0
1
2
3
4
5
6
7
Symbol
EIPLLCK1
EIPLLCK2
EIPLLCK3
EIPLLCK4
EIPLLCK5
EIPLLCK6
EIPLLCK7
EIPLLCK8
Description
Enable Transmit Framer 1’s Internal PLLCK Clock Synthesizer.
Enable Transmit Framer 2’s Internal PLLCK Clock Synthesizer.
Enable Transmit Framer 3’s Internal PLLCK Clock Synthesizer.
Enable Transmit Framer 4’s Internal PLLCK Clock Synthesizer.
Enable Transmit Framer 5’s Internal PLLCK Clock Synthesizer.
Enable Transmit Framer 6’s Internal PLLCK Clock Synthesizer.
Enable Transmit Framer 7’s Internal PLLCK Clock Synthesizer.
Enable Transmit Framer 8’s Internal PLLCK Clock Synthesizer.
Framer Register Architecture
REGBANK1—REGBANK8 contain the status and pro-
grammable control registers for the framer and system
CHI interface channels FRM1—FRM8. The base
address for REGBANK1—REGBANK8 is Y00 (hex),
where Y = 2—9 for FRM1—FRM8, respectively. Within
these register banks, the bit map is identical for
FRM1—FRM8.
The framer registers are structures as shown in Table
68. Default values are given in the individual register
definition tables.
Table 68. Framer Status and Control Blocks
Address Range (Hexadecimal)
* The most significant digit, designated by Y, is used to identify each
framer (for framer 1—framer 8, Y = 2—9, respectively).
The complete register map for the framer is given in
Table 182—Table 186. The address of the registers is
shown in the table title with the most significant digit,
designated by Y, used to identify each framer (for
framer 1—framer 8, Y = 2—9, respectively).
All status registers are clocked with the internal framer
receive line clock (RFRMCK).
Bits in status registers FRM_SR1 and FRM_SR7 are
set at the onset of the condition and are cleared on
read when the given condition is no longer present.
These registers can generate interrupts if the corre-
sponding register bits are enabled in interrupt enable
registers FRM_PR0—FRM_PR7.
On all 16-bit counter registers (FRM_SR8—
FRM_SR51), both bytes are cleared only after reading
both bytes. These status registers are two byte register
pairs. These register pairs must be read in succession,
with the lower byte read first followed by a read of
higher byte. Once a read is initiated on one of the
bytes, the updating of that counter is disabled and
remains disabled until both bytes are read. All events
during this interval are lost. Updating of the counter
registers is stopped when all of the bits are set to 1.
Updating resumes after the registers are cleared on
read. These register pairs may be read in any order,
but they must be read in pairs, i.e., a read of 1 byte
must be followed immediately by a read of the remain-
ing byte of the pair.
Status registers FRM_SR0—FRM_SR63 are clear-on-
read (COR) registers. These registers are cleared by
the framer internal received line clock (RFRMCK). At
least two RFRMCK cycles (1.3 μs for DS1 and 1.0 μs
for CEPT) must be allowed between successive reads
of the same COR register to allow it to properly clear.
Framer Register Block
Status Registers (COR) (Y00—Y3F)*
Receive Signaling Registers (Y40—Y5F)*
Parameter (Configuration) Registers (Y60—YA6)*
Transmit Signaling Registers (YE0—YFF)*
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