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參數(shù)資料
| 型號： | TFRA08C13 |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 69/188頁 |
| 文件大?。?/td> | 3047K |
| 代理商： | TFRA08C13 |
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Lucent Technologies Inc.
69
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring
(continued)
Table 28. Alarm Indication Signal Conditions
I
The
SLIP
condition (FRM_SR3 bit 6 and bit 7). SLIP is defined as the state in which the receive elastic store
buffer’s write address pointer from the receive framer and the read address pointer from the transmit concentra-
tion highway interface are equal
*
.
— The negative slip (Slip-N) alarm indicates that the receive line clock (RLCK) - transmit CHI clock (CHICK)
monitoring circuit detects a state of overflow caused by RLCK and CHICK being out of phase-lock and the
period of the received frame being less than that of the system frame. One system frame is deleted.
— The positive slip (Slip-P) alarm indicates the line clock (RLCK) - transmit CHI clock (CHICK) monitoring circuit
detects a state of underflow caused by RLCK and CHICK being out of phase-lock and the period of the
received frame being greater than that of the system frame. One system frame is repeated.
I
The
loss of framer receive clock
(LORLCK, pin G23). The LORLCK alarm is asserted high when an interval of
250 ms has expired with no transition of RLCK (pin see Table 2. Pin Descriptions) detected. The alarm is dis-
abled on the first transition of RLCK. Bit 0—bit 2 of global register 8 (GREG8) determine which framer sources
the LORLCK pin (see Table 69 Interrupt Status Register (FRM_SR0) (Y00)).
I
The
loss of PLL clock
(LOPLLCK, pin F25). LOPLLCK alarm is asserted high when an interval of 250 ms has
expired with no transition of PLLCK (pin see Table 2 . Pin Descriptions) detected. The alarm is disabled 250 μs
after the first transition of PLLCK. Timing for LOPLLCK is shown in Figure 26. Bit 0—bit 2 of global register 8
(GREG8) determine which framer sources the LOPLLCK pin (see Table 69).
5-6564(F).a
Figure 26. Timing for Generation of LOPLLCK (Pin F25)
* After a reset, the read and write pointers of the receive path elastic store will be set to a known state.
Framing Format
T1
Remote Frame Alarm Format
Loss of frame alignment occurs and the incoming signal has two or fewer zeros in each of
two consecutive double frame periods (386 bits).
As described in ETSI ETS 300 233: May 1994, Section 8.2.2.4, loss of frame alignment
occurs and the framer receives a 512 bit period containing two or less binary zeros. This
is enabled by setting register FRM_PR10 bit 1 to 0.
As described in ITU Rec. G.775, the incoming signal has two or fewer zeros in each of
two consecutive double frame periods (512 bits). AIS is cleared if each of two consecutive
double frame periods contains three or more zeros or frame alignment signal (FAS) has
been found. This is enabled by setting register FRM_PR10 bit 1 to 1.
CEPT ETSI
CEPT ITU
PLLCK
LOPLLCK
CHICK
250
μ
s
250
μ
s
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TFRA08C13-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:TFRA08C13 OCTAL T1/E1 Framer |
| TFRA28J133BAL-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| TFRA84J13 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| TFRA84J131BL-3-DB | 制造商:LSI Corporation 功能描述:Framer DS0/DS1/DS2/DS3/E1/E2/E3 1.5V/3.3V 909-Pin BGA |
| TFRA84J13DS0 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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