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參數(shù)資料
| 型號： | TFRA08C13 |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 93/188頁 |
| 文件大?。?/td> | 3047K |
| 代理商： | TFRA08C13 |
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Lucent Technologies Inc.
93
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link
(continued)
Transmit FDL FIFO
Transmit FDL data is loaded into the 64-byte transmit
FIFO via the transmit FDL data register, FDL_PR4. The
transmit FDL status register indicates how many addi-
tional bytes can be added to the transmit FIFO. The
transmit FDL interrupt trigger level register FDL_PR3
bit 0—bit 5 (FTIL) can be programmed to tailor service
time intervals to the system environment. The transmit-
ter empty interrupt bit is set in the FDL interrupt status
register FDL_SR0 bit 1 (FTEM) when the transmit
FIFO has sufficient empty space to add the number of
bytes specified in register FDL_PR3 bit 0—bit 5. There
is no interrupt indicated for a transmitter overrun that is
writing more data than empty spaces exist. Overrun-
ning the transmitter causes the last valid data byte writ-
ten to be repeatedly overwritten, resulting in missing
data in the frame.
Data associated with multiple frames can be written to
the transmit FIFO by the controlling microprocessor.
However, all frames must be explicitly tagged with a
transmit frame complete, register FDL_PR3 bit 7
(FTFC), or a transmit abort, register FDL_PR3 bit 6
(FTABT). The FTFC is tagged onto the last byte of a
frame written into the transmitter FIFO and instructs the
transmitter to end the frame and attach the CRC and
closing flag following the tagged byte. Once written, the
FTFC cannot be changed by another write to register
FDL_PR3. If FTFC is not written before the last data
byte is read out for transmission, an underrun occurs
(FDL_SR0 bit 2). When the transmitter has completed
a frame, with a closing flag or an abort sequence, reg-
ister FDL_SR0 bit 0 (FTDONE) is set to 1. An interrupt
is generated if FDL_PR2 bit 0 (FTDIE) is set to 1.
Sending 1-Byte Frames
Sending 1-byte frames with an empty transmit FIFO is
not recommended. If the FIFO is empty, writing two
data bytes to the FIFO before setting FTFC provides a
minimum of eight TFDLCK periods to set FTFC. When
1 byte is written to the FIFO, FTFC must be written
within 1 TFDLCK period to guarantee that it is effective.
Thus, 1-byte frames are subject to underrun aborts.
One-byte frames cannot be aborted with FTABT. Plac-
ing the transmitter in ones-idle mode, register
FDL_PR0 bit 1 (FLAGS) = 0, lessens the frequency of
underruns. If the transmit FIFO is not empty, then
1-byte frames present no problems.
Transmitter Underrun
After writing a byte to the transmit queue, the user has
eight TFDLCK cycles in which to write the next byte
before a transmitter underrun occurs. An underrun
occurs when the transmitter has finished transmitting
all the bytes in the queue, but the frame has not yet
been closed by setting FTFC. When a transmitter
underrun occurs, the abort sequence is sent at the end
of the last valid byte transmitted. A FTDONE interrupt
is generated, and the transmitter reports an underrun
abort until the interrupt status register is read.
Using the Transmitter Status and Fill Level
The transmitter-interrupt level bits, register FDL_PR3
bit 0—bit 5, allow the user to instruct the FDL HDLC
block to interrupt the host processor whenever the
transmitter has a predetermined number of empty loca-
tions. The number of locations selected determines the
time between transmitter empty, register FRM_SR0 bit
1 (FTEM), interrupts. The transmitter status bits, regis-
ter FDL_SR1, report the number of empty locations in
the FDL transmitter FIFO. The transmitter empty
dynamic bit, register FDL_SR1 bit 7 (FTED), like the
FTEM interrupt bit, is set to 1 when the number of
empty locations is less than or equal to the pro-
grammed empty level. FTED returns to 0 when the
transmitter is filled to above the programmed empty
level. Polled interrupt systems can use FTED to deter-
mine when they can write to the FDL transmit FIFO.
Transparent Mode
The FDL HDLC block can be programmed to operate in
the transparent mode by setting register FDL_PR9 bit 6
(FTRANS) to 1. In the transparent mode of operation,
no HDLC processing is performed on user data. The
transparent mode can be exited at any time by setting
FDL_PR9 bit 6 (FTRANS) to 0. It is recommended that
the transmitter be disabled when changing in and out of
transparent mode. The transmitter should be reset by
setting FDL_PR1 bit 5 (FTR) to 1 whenever the mode
is changed.
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