參數(shù)資料
型號(hào): TMDXCNCD28069ISO
廠商: Texas Instruments
文件頁數(shù): 12/174頁
文件大?。?/td> 0K
描述: EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
主要目的: 接口,RS232,GPIO
嵌入式: 是,MCU,32 位
已用 IC / 零件: TMS320F2806x
已供物品:
(
)
CLKSRG
CLKG =
1 + CLKGDV
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.14 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
Compatible to McBSP in TMS320C54x/ TMS320C55x DSP devices
Full-duplex communication
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
Works with SPI-compatible devices
The following application interfaces can be supported on the McBSP:
T1/E1 framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
SPI
McBSP clock rate,
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit.
NOTE
See Section 5 for maximum I/O pin toggling speed.
NOTE
On the 80-pin package, only the clock-stop mode (SPI) of the McBSP is supported.
Copyright 2010–2012, Texas Instruments Incorporated
Peripheral and Electrical Specifications
109
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