參數(shù)資料
型號: TMDXCNCD28069ISO
廠商: Texas Instruments
文件頁數(shù): 20/174頁
文件大小: 0K
描述: EVAL PICCOLO CONTROLCARD
標準包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
主要目的: 接口,RS232,GPIO
嵌入式: 是,MCU,32 位
已用 IC / 零件: TMS320F2806x
已供物品:
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M35
M37
M40
M39
M38
M34
LSB
MSB
M41
M42
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
Table 5-40. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
NO.
UNIT
MIN
MAX
MIN MAX
M39
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
30
8P – 10
ns
M40
th(CKXH-DRV)
Hold time, DR valid after CLKX high
1
8P – 10
ns
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
16P + 10
ns
M42
tc(CKX)
Cycle time, CLKX
2P(1)
16P
ns
(1)
2P = 1/CLKG
Table 5-41. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
over recommended operating conditions (unless otherwise noted)
MASTER
SLAVE
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
M34
th(CKXL-FXL)
Hold time, FSX low after CLKX low
P
ns
M35
td(FXL-CKXH)
Delay time, FSX low to CLKX high
2P(1)
ns
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
P + 6
7P + 6
ns
from CLKX low
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1)
2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 90 MHz, CLKX maximum
frequency is LSPCLK/16; that is, 5.625 MHz and P = 11.11 ns.
Figure 5-36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
116
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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