SPICTL.0 SPI INT FLAG SPI INT ENA SPISTS.6 S Clock Polarity Talk LSPCLK SPI Bit Rate State Control Clock Phase Receiver Overrun Flag <" />
參數(shù)資料
型號: TMDXCNCD28069ISO
廠商: Texas Instruments
文件頁數(shù): 174/174頁
文件大小: 0K
描述: EVAL PICCOLO CONTROLCARD
標準包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
主要目的: 接口,RS232,GPIO
嵌入式: 是,MCU,32 位
已用 IC / 零件: TMS320F2806x
已供物品:
S
SPICTL.0
SPI INT FLAG
SPI INT
ENA
SPISTS.6
S
Clock
Polarity
Talk
LSPCLK
SPI Bit Rate
State Control
Clock
Phase
Receiver
Overrun Flag
SPICTL.4
Overrun
INT ENA
SPICCR.3 - 0
SPIBRR.6 - 0
SPICCR.6
SPICTL.3
SPIDAT.15 - 0
SPICTL.1
M
S
M
Master/Slave
SPISTS.7
SPIDAT
Data Register
M
S
SPICTL.2
SPI Char
SPISIMO
SPISOMI
SPICLK
SW2
S
M
S
SW3
To CPU
M
SW1
RX FIFO _0
RX FIFO _1
-----
RX FIFO _3
TX FIFO Registers
TX FIFO _0
TX FIFO _1
-----
TX FIFO _3
RX FIFO Registers
16
TX Interrupt
Logic
RX Interrupt
Logic
SPIINT
SPITX
SPIFFOVF
FLAG
SPIFFRX.15
TX FIFO Interrupt
RX FIFO Interrupt
SPIRXBUF
SPITXBUF
SPIFFTX.14
SPIFFENA
SPISTE
16
0
1
2
3
0
1
2
3
4
5
6
TW
SPIPRI.0
TRIWIRE
SPIPRI.1
STEINV
SPIRXBUF
Buffer Register
SPITXBUF
Buffer Register
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
Figure 5-26 is a block diagram of the SPI in slave mode.
A.
SPISTE is driven low by the master for a slave device.
Figure 5-26. SPI Module Block Diagram (Slave Mode)
5.12.1 Serial Peripheral Interface (SPI) Master Mode Electrical Data/Timing
Table 5-29 lists the master mode timing (clock phase = 0) and Table 5-30 lists the master mode timing
(clock phase = 1). Figure 5-27 and Figure 5-28 show the timing waveforms.
Copyright 2010–2012, Texas Instruments Incorporated
Peripheral and Electrical Specifications
99
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