參數(shù)資料
型號: TMDXCNCD28069ISO
廠商: Texas Instruments
文件頁數(shù): 16/174頁
文件大小: 0K
描述: EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
主要目的: 接口,RS232,GPIO
嵌入式: 是,MCU,32 位
已用 IC / 零件: TMS320F2806x
已供物品:
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.14.1 Multichannel Buffered Serial Port (McBSP) Electrical Data/Timing
5.14.1.1 McBSP Transmit and Receive Timing
Table 5-36. McBSP Timing Requirements(1)(2)
NO.
MIN
MAX
UNIT
McBSP module clock (CLKG, CLKX, CLKR) range
1
kHz
20(3)(4)
MHz
McBSP module cycle time (CLKG, CLKX, CLKR) range
50(4)
ns
1
ms
M11
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
ns
M12
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P – 7
ns
M13
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
7
ns
M14
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
7
ns
M15
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int
18
ns
CLKR ext
2
M16
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
0
ns
CLKR ext
6
M17
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
18
ns
CLKR ext
2
M18
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
0
ns
CLKR ext
6
M19
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
18
ns
CLKX ext
2
M20
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
0
ns
CLKX ext
6
(1)
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2)
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG
≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3)
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (20 MHz).
(4)
Maximum McBSP module clock frequency decreases to 10 MHz for internal CLKR.
112
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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