參數(shù)資料
型號: TMDXCNCD28069ISO
廠商: Texas Instruments
文件頁數(shù): 49/174頁
文件大小: 0K
描述: EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
主要目的: 接口,RS232,GPIO
嵌入式: 是,MCU,32 位
已用 IC / 零件: TMS320F2806x
已供物品:
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.23 General-Purpose Input/Output (GPIO) MUX
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition
to providing individual pin bit-banging I/O capability.
The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral
Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 5-64 shows the
GPIO register mapping.
Table 5-64. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
0x6F80
2
GPIO A Control Register (GPIO0 to 31)
GPAQSEL1
0x6F82
2
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2
0x6F84
2
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1
0x6F86
2
GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2
0x6F88
2
GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR
0x6F8A
2
GPIO A Direction Register (GPIO0 to 31)
GPAPUD
0x6F8C
2
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPBCTRL
0x6F90
2
GPIO B Control Register (GPIO32 to 44)
GPBQSEL1
0x6F92
2
GPIO B Qualifier Select 1 Register (GPIO32 to 44)
GPBQSEL2
0x6F94
2
GPIO B Qualifier Select 2 Register
GPBMUX1
0x6F96
2
GPIO B MUX 1 Register (GPIO32 to 44)
GPBMUX2
0x6F98
2
GPIO B MUX 2 Register (GPIO50 to 58)
GPBDIR
0x6F9A
2
GPIO B Direction Register (GPIO32 to 44)
GPBPUD
0x6F9C
2
GPIO B Pull Up Disable Register (GPIO32 to 44)
AIOMUX1
0x6FB6
2
Analog, I/O mux 1 register (AIO0 to AIO15)
AIODIR
0x6FBA
2
Analog, I/O Direction Register (AIO0 to AIO15)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
0x6FC0
2
GPIO A Data Register (GPIO0 to 31)
GPASET
0x6FC2
2
GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR
0x6FC4
2
GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE
0x6FC6
2
GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT
0x6FC8
2
GPIO B Data Register (GPIO32 to 44)
GPBSET
0x6FCA
2
GPIO B Data Set Register (GPIO32 to 44)
GPBCLEAR
0x6FCC
2
GPIO B Data Clear Register (GPIO32 to 44)
GPBTOGGLE
0x6FCE
2
GPIO B Data Toggle Register (GPIO32 to 44)
AIODAT
0x6FD8
2
Analog I/O Data Register (AIO0 to AIO15)
AIOSET
0x6FDA
2
Analog I/O Data Set Register (AIO0 to AIO15)
AIOCLEAR
0x6FDC
2
Analog I/O Data Clear Register (AIO0 to AIO15)
AIOTOGGLE
0x6FDE
2
Analog I/O Data Toggle Register (AIO0 to AIO15)
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL
0x6FE1
1
XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL
0x6FE2
1
XINT3 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL
0x6FE8
2
LPM GPIO Select Register (GPIO0 to 31)
NOTE
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn
and GPxQSELn registers occurs to when the action is valid.
142
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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