參數資料
型號: TMDXCNCD28069ISO
廠商: Texas Instruments
文件頁數: 22/174頁
文件大?。?/td> 0K
描述: EVAL PICCOLO CONTROLCARD
標準包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
主要目的: 接口,RS232,GPIO
嵌入式: 是,MCU,32 位
已用 IC / 零件: TMS320F2806x
已供物品:
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M54
M58
M56
M53
M55
M59
M57
LSB
MSB
M60
M61
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
Table 5-44. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
NO.
UNIT
MIN
MAX
MIN
MAX
M58
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
30
8P – 10
ns
M59
th(CKXL-DRV)
Hold time, DR valid after CLKX low
1
8P – 10
ns
M60
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
16P + 10
ns
M61
tc(CKX)
Cycle time, CLKX
2P(1)
16P
ns
(1)
2P = 1/CLKG
Table 5-45. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1)
over recommended operating conditions (unless otherwise noted)
MASTER
SLAVE
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
M53
th(CKXH-FXL)
Hold time, FSX low after CLKX high
P
ns
M54
td(FXL-CKXL)
Delay time, FSX low to CLKX low
2P(1)
ns
M55
td(CLKXH-DXV)
Delay time, CLKX high to DX valid
–2
0
3P + 6
5P + 20
ns
M56
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last
P + 6
7P + 6
ns
data bit from CLKX high
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1)
2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 90 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 5.625 MHz and P = 11.11 ns.
Figure 5-38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
118
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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