參數(shù)資料
型號： TMDXCNCD28069ISO
廠商： Texas Instruments
文件頁數(shù)： 5/174頁
文件大?。?/td> 0K
描述： EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝： 1
系列： TMS320F2806x, Piccolo™, C2000™
主要目的： 接口，RS232，GPIO
嵌入式： 是，MCU，32 位
已用 IC / 零件： TMS320F2806x
已供物品： 板
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
Table 5-30. SPI Master Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)(5)
SPI WHEN (SPIBRR + 1) IS EVEN
SPI WHEN (SPIBRR + 1) IS ODD
OR SPIBRR = 0 OR 2
AND SPIBRR > 3
NO.
UNIT
MIN
MAX
MIN
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
ns
2
tw(SPCH)M
Pulse duration, SPICLK high
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc (LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
ns
(clock polarity = 0)
tw(SPCL))M
Pulse duration, SPICLK low
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc (LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO
(clock polarity = 1)
3
tw(SPCL)M
Pulse duration, SPICLK low
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO)
ns
(clock polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO)
(clock polarity = 1)
6
tsu(SIMO-SPCH)M
Setup time, SPISIMO data valid
0.5tc(SPC)M – 10
ns
before SPICLK high
(clock polarity = 0)
tsu(SIMO-SPCL)M
Setup time, SPISIMO data valid
0.5tc(SPC)M – 10
before SPICLK low
(clock polarity = 1)
7
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – 10
ns
SPICLK high (clock polarity = 0)
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – 10
SPICLK low (clock polarity = 1)
10
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
26
ns
SPICLK high (clock polarity = 0)
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
26
SPICLK low (clock polarity = 1)
11
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
0.25tc(SPC)M – 10
0.5tc(SPC)M – 10
ns
SPICLK high (clock polarity = 0)
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
0.25tc(SPC)M – 10
0.5tc(SPC)M – 10
SPICLK low (clock polarity = 1)
(1)
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2)
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4)
tc(LCO) = LSPCLK cycle time
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
102
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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