參數(shù)資料
型號: TMDXCNCD28069ISO
廠商: Texas Instruments
文件頁數(shù): 19/174頁
文件大小: 0K
描述: EVAL PICCOLO CONTROLCARD
標準包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
主要目的: 接口,RS232,GPIO
嵌入式: 是,MCU,32 位
已用 IC / 零件: TMS320F2806x
已供物品:
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
M30
M31
DR
M28
M24
M29
M25
LSB
MSB
M32
M33
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.14.1.2 McBSP as SPI Master or Slave Timing
Table 5-38. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
NO.
UNIT
MIN
MAX
MIN
MAX
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
30
8P – 10
ns
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
1
8P – 10
ns
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
8P + 10
ns
M33
tc(CKX)
Cycle time, CLKX
2P(1)
16P
ns
(1)
2P = 1/CLKG
Table 5-39. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
over recommended operating conditions (unless otherwise noted)
MASTER
SLAVE
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2P(1)
ns
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
P
ns
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following
6
6P + 6
ns
last data bit from FSX high
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1)
2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 90 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 5.625 MHz and P = 11.11 ns.
Figure 5-35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Copyright 2010–2012, Texas Instruments Incorporated
Peripheral and Electrical Specifications
115
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