參數(shù)資料
型號： TMDXCNCD28069ISO
廠商： Texas Instruments
文件頁數(shù)： 122/174頁
文件大?。?/td> 0K
描述： EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝： 1
系列： TMS320F2806x, Piccolo™, C2000™
主要目的： 接口，RS232，GPIO
嵌入式： 是，MCU，32 位
已用 IC / 零件： TMS320F2806x
已供物品： 板
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
The PLL-based clock module provides four modes of operation:
INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide
the clock for the Watchdog block, core and CPU-Timer 2
INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide
the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be
independently chosen for the Watchdog block, core and CPU-Timer 2.
Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external
crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to
the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 2-5 for details.
External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to
be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin.
Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected
as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit
disables this clock input (forced low). If the clock source is not used or the respective pins are used as
GPIOs, the user should disable at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that
clock source must be disabled (using the CLKCTL register) before switching clocks.
Table 2-17. Possible PLL Configuration Modes
CLKIN AND
PLL MODE
REMARKS
PLLSTS[DIVSEL]
SYSCLKOUT
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
0, 1
OSCCLK/4
PLL Off
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
2
OSCCLK/2
before entering this mode. The CPU clock (CLKIN) is derived directly from the
3
OSCCLK/1
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external
0, 1
OSCCLK/4
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
PLL Bypass
2
OSCCLK/2
while the PLL locks to a new frequency after the PLLCR register has been
3
OSCCLK/1
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0, 1
OSCCLK * n/4
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLL Enable
2
OSCCLK * n/2
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
3
OSCCLK * n/1
Copyright 2010–2012, Texas Instruments Incorporated
Device Overview
51
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