
www.ti.com
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 6-83. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
01C8 0640
TX0CP
01C8 0644
TX1CP
01C8 0648
TX2CP
01C8 064C
TX3CP
01C8 0650
TX4CP
01C8 0654
TX5CP
01C8 0658
TX6CP
01C8 065C
TX7CP
01C8 0660
RX0CP
01C8 0664
RX1CP
01C8 0668
RX2CP
01C8 066C
RX3CP
01C8 0670
RX4CP
01C8 0674
RX5CP
01C8 0678
RX6CP
01C8 067C
RX7CP
202
Peripheral and Electrical Specifications
Submit Documentation Feedback