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2
Device Overview
2.1 Device Characteristics
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 2-1
provides an overview of the TMS320DM6443 SoC. The table shows significant features of the
device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the
C64x+ DSP, and the package type with pin count.
Table 2-1. Characteristics of the Processor
HARDWARE FEATURES
DDR2 Memory Controller
DM6443
DDR2 (16/32-bit bus width)
Asynchronous (8/16-bit bus width) RAM, Flash
(NOR,NAND)
Compact Flash
MMC/SD with secure data input/output (SDIO)
SmartMedia/xD
64 independent channels
8 QDMA channels
2 64-Bit General Purpose (each configurable as 2
separate 32-bit timers)
1 64-Bit Watch Dog
3 (one with RTS and CTS flow control)
1 (supports 2 slave devices)
1 (Master/Slave)
1
Asynchronous EMIF (EMIFA)
Flash Cards
EDMA
Timers
UART
SPI
I
2
C
Audio Serial Port [ASP]
10/100 Ethernet MAC with Management Data
Input/Output
VLYNQ
HPI
General-Purpose Input/Output Port
PWM
ATA/CF
Peripherals
Not all peripherals pins are
available at the same time
(for more detail, see the
Device Configurations
section).
1
1
1 (16-bit multiplexed address/data)
Up to 71
3 outputs
1 (ATA/ATAPI-6)
Resizer
1 Output (VPBE)
High Speed Device
High Speed Host
160KB RAM, 8KB ROM
Configurable Video Port
USB 2.0
Size (Bytes)
DSP
ARM
32KB L1 Program (L1P)/Cache (up to 32KB)
80KB L1 Data (L1D)/Cache (up to 32KB)
64KB Unified Mapped RAM/Cache (L2)
On-Chip Memory
Organization
16KB I-cache
8KB D-cache
16KB RAM
8KB ROM
CPU ID + CPU Rev ID
C64x+ Megamodule
Revision
Control Status Register (CSR.[31:16])
Revision ID Register (MM_REVID[15:0])
(address location: 0x0181 2000)
JTAGID Register
(address location: 0x01C4 0028)
0x1000
0x0000
JTAG BSDL_ID
0x0B70 002F
DSP 594 MHz
ARM 297 MHz
CPU Frequency (Maximum)
MHz
DM6443 -594
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Device Overview
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