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TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 2-22. PWM0, PWM1, PWM2 Terminal Functions
SIGNAL
NAME
TYPE
(1)
OTHER
(2)
DESCRIPTION
NO.
PWM2
PWM2/
B2/
GPIO47
This pin is multiplexed between PWM2, VPBE, and GPIO.
For PWM2, it is output PWM2.
A15
I/O/Z
DV
DD18
PWM1
PWM1/
R2/
GPIO46
This pin is multiplexed between PWM1, VPBE, and GPIO.
For PWM1, it is output PWM1.
B15
I/O/Z
DV
DD18
PWM0
PWM0/
GPIO45
This pin is multiplexed between PWM0 and GPIO.
For PWM0, it is output PWM0.
C15
I/O/Z
DV
DD18
(1)
(2)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
Specifies the operating I/O supply voltage for each signal
Table 2-23. ATA/CF Terminal Functions
SIGNAL
NAME
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NO.
ATA/CF
SPI_EN1/
HDDIR/
GPIO42
GPIO50/
ATA_CS0
GPIO51/
ATA_CS1
EM_R/W/
INTRQ
EM_WAIT/
(RDY/BSY)/
IORDY
EM_OE/
(RE)/
(IORD)/
DIOR
EM_WE
(WE)
(IOWR)/
DIOW
DMACK/
UART_TXD1
DMARQ/
This pin is multiplexed between SPI, ATA, and GPIO.
For ATA, it is buffer direction control output HDDIR.
B2
I/O/Z
DV
DD18
This pin is multiplexed between GPIO and ATA/CF.
In ATA mode, it is ATA/CF chip select output ATA_CS0.
This pin is multiplexed between GPIO and ATA/CF.
In ATA mode, it is ATA/CF chip select output ATA_CS1.
This pin is multiplexed between EMIFA and ATA/CF.
For ATA/CF, it is interrupt request input INTRQ.
J5
O
DV
DD18
H1
O
DV
DD18
G3
I
DV
DD18
IPU
DV
DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.
For ATA/CF, it is IO Ready input IORDY.
F1
I
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.
For CF, it is read strobe output (IORD).
For ATA, it is read strobe output DIOR.
H4
O
DV
DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.
For CF, it is write strobe output (IOWR).
For ATA, it is write strobe output DIOW.
G2
O
DV
DD18
This pin is multiplexed between ATA/CF and UART1.
For ATA/CF, it is DMA acknowledge output DMACK.
This pin is multiplexed between ATA/CF and UART1.
For ATA/CF, it is DMA request DMARQ input.
H3
O
DV
DD18
IPD
DV
DD18
G1
O
(1)
(2)
(3)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k
resistor should be used.)
Specifies the operating I/O supply voltage for each signal
Device Overview
46
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