參數(shù)資料
型號: TNETA1560
廠商: Texas Instruments, Inc.
英文描述: ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設裝置帶SBUS主機接口)
中文描述: 自動柜員機分段和重組與SBus主機接口(自動柜員機分段和重設裝置帶SBU的主機接口設備)
文件頁數(shù): 13/40頁
文件大小: 804K
代理商: TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics (see Note 6 and Figure 7)
NO.
MIN
TYP
MAX
UNIT
1
td(LBPHYCS)1
td(LBPHYCS)2
Delay time, LBRD
to LBPHYCS
40
ns
2
Delay time, LBREADY
to LBPHYCS
120
ns
The typical values are given for operation with a 25-MHz SBus clock.
NOTE 6: If LBREADY does not go active low within eight SBus clocks after LBPHYCS goes active low, TNETA1560 latches in the data on the
LBD7–LBD0 bus and terminates the read operation.
LBRW
(output)
LBRD
(output)
LBADDR15–
LBADDR0
(output)
LBD7–
LBD0
(input)
LBREADY
(input)
LBPHYCS
(output)
1
2
Figure 7. Local-Bus-Interface Read Operation (TNETA1560 as Slave)
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