參數(shù)資料
型號(hào): TNETA1560
廠商: Texas Instruments, Inc.
英文描述: ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述: 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口(自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備)
文件頁數(shù): 32/40頁
文件大?。?/td> 804K
代理商: TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
BWG index (bits 7 – 0)
The only item that is posted to the transmit completion ring when the SAR completes transmission of a packet
is the BWG index. This is adequate for the host to locate the transmit-buffer pointers to the buffer locations where
data for the packet was stored and reclaim the buffer space.
receive free-buffer-ring format
Table 9 shows the composition of each free-buffer-ring entry. Each of the two rings has 256 entries. The host
places free-buffer pointers in each ring. The SAR removes a pointer when it starts processing each new packet
from the link.
Table 9. Receive Free-Buffer-Ring Summary
ENTRY
DESCRIPTION
Word 0
OWN (bit 31)
Unused (bits 30 – 28)
Start-of-buffer pointer (bits 27 – 0)
Word 1
Reserved
Word 2
Reserved
Word 3
Reserved
RX free-buffer-ring word 0
OWN (bit 31)
Each free-buffer-ring entry is owned by the SAR when the OWN bit is set and it is owned by the host when the
OWN bit is zero. The host sets the OWN bit for new entries placed in the free-buffer rings. The SBus SAR uses
the next free-buffer-ring entry in the respective ring if the OWN bit is set. The SBus SAR clears the OWN bit after
acquiring the buffer and releasing the ring location to the host. The buffer is not freed until a packet is posted
to the receive completion ring. If the OWN bit is not set when the SAR polls a free-buffer ring for a new entry,
a status bit is set in the hardware-status register and an interrupt is generated if the error condition is unmasked.
start-of-buffer pointer (bits 27 – 0)
A pointer to a buffer, aligned to a 16-byte boundary, is the only information placed in each free-buffer ring.
receive DMA block
The SAR supports 1024 receive DMA-channel entries with each containing eight words. Each DMA channel
represents a VCI on which data is received, and DMA entries in the control memory are indexed by incoming
VCIs. The SAR initiates all transactions affecting the DMA table, except those required for one-time
configuration of a channel in word 3, during normal operation based on the header of cells received from the
link. Table 10 summarizes a receive DMA-channel entry.
Table 10. Receive DMA-Virtual-Channel Entry
ENTRY
DESCRIPTION
STATIC/DYNAMIC
Word 0
Control, status, EFCN cell count, current packet length
Dynamic
Word 1
Current buffer pointer – 28 bits
Dynamic
Word 2
Start-of-buffer pointer – 28 bits
Static
Word 3
Control, packet length
Static
Word 4
Reserved
Word 5
AAL5 partial CRC – 32 bits
Dynamic
Word 6
Reserved
Word 7
Reserved
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