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參數(shù)資料
| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組與SBus主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
end of chain (EOC) (bit 29)
The EOC bit indicates that this is the last buffer of a packet. Every packet has at least one buffer with the EOC
bit set.
AAL type – AAL5 indicator (bit 27)
The AAL-type bit is set to zero to indicate that the packet described in this descriptor-ring entry is an AAL5 packet.
This bit is a configuration item rather than a bit carrying state information. This bit is set in every buffer of a packet,
and the software driver ensures that all buffers within a packet use the same AAL type.
current-packet length (bits 26 – 16)
The SBus SAR increments this two’s-complement value with every cell transmitted until the counter is equal
to zero, which indicates to the SAR that the entire packet has been transmitted.
current-buffer length (bits 15 – 0)
The buffer-length field specifies the number of remaining bytes in the buffer currently being processed in this
BWG. The SAR adds to the value of this two’s-complement field with every transfer of payload data to the XMB
until it is equal to zero, which indicates to the SAR that all the bytes in this buffer are processed and queued
for transmission.
TX DMA word 1 – current-buffer pointer
Byte-aligned current-buffer pointer (bits 31 – 0)
The current-buffer pointer is copied directly from the start-of-buffer pointer in the corresponding transmit
data-descriptor-ring entry at the start of each new buffer. The field is 32 bits, which implies that the buffer is
aligned to a byte boundary. The pointer is adjusted to point to the current location after each transfer of payload
data from the host to the XMB.
TX DMA word 2 – ATM header
PTI2 (bits 31 – 29)
VPI (bits 27 – 20) VCI (bits 19 – 4)
CLP2 (bit 28)
PTI1 (bits 3 – 1)
CLP1 (bit 0)
The 4-byte ATM header field is copied directly from the corresponding transmit data-descriptor entry at the start
of each new packet. Bits (28 – 0) are concatenated to the 4-bit GFC field that is set to zero for every cell in the
packet except the last one. Bits (31 – 28) provide the PTI and CLP fields in the last cell of each packet.
TX DMA word 3 – configuration
BWG_ON (bit 31)
Unused (bits 30 – 0)
This bit allows the host to enable data transmission on a per-BWG basis. The BWG_ON bit from the current
BWG index is examined by the SAR on each cell opportunity. BWG_ON (31) is directly set by the host to indicate
that the BWG is enabled and that normal data processing is followed. If the bit is zero, no processing of transmit
data on the BWG is performed and an idle cell is transmitted on the link. This idle cell is used by the host to
respond to congestion indicators.
TX DMA word 4 – descriptor-ring address
TX data-descriptor-ring pointer (bits 31 – 12)
TX descriptor-ring entry (bits 11 – 4)
0000 (bits 3 – 0)
This pointer is a direct DVMA address to the location of the current entry (there are 256 entries in each ring)
in the corresponding transmit data-descriptor ring (one of 255 rings) for this BWG. Each descriptor ring is aligned
to a 4K-byte boundary in host memory with each entry aligned to a 16-byte boundary.
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