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| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 38/40頁 |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
TX_comp_notav (bit 5)
The transmit completion-ring not-available bit is set when the next descriptor in the receive completion ring has
not been released by the host. This is indicated when the OWN bit in the entry is zero. The transmit-freeze bit
is set when this bit is set, disabling all transmit operation until the transmit-freeze bit is cleared via an active
command from the host.
TX_freeze (bit 6)
The transmit-freeze bit is set when the TX_comp_notav bit is set, disabling all transmit operation until the
transmit-freeze bit is cleared via an active command from the host. This has the same effect on the transmit
circuitry as disabling the enable-transmit bit.
RX_freeze (bit 7)
The receive-freeze bit is set when the RX_comp_notav bit is set, disabling all receive operation until the receive
freeze bit is cleared via an active command by the host. The buffer that could not be posted is effectively lost,
and the host must find some way to recover it while the freeze is in operation. The receive-freeze indicator has
the same effect on the receive path as disabling the enable-receive bit.
SB_err_ack (bit 8)
The SBus-error-acknowledgment bit is set to indicate that the SAR detected the SBus-error-acknowledgment
signal; i.e., SBACK2 – SBACK0 set to 110 during the SBus DMA cycle. The SAR then terminates the ongoing
master-bus cycle, even if it is a burst transfer, and freezes all DMA-channel operation until a hardware or
software reset. This is a fatal error.
SB_lerr (bit 9)
The SBus-late-error bit is set to indicate that the SAR detected the SBus-late-error (SBLERR) signal during the
SBus DMA cycle. The SBus SAR then terminates the ongoing master-bus cycle unless it is a burst transfer, in
which case, it completes the burst. It then freezes all DMA-channel operation until a hardware or software reset.
This is a fatal error.
LB_intr (bit 10)
The LBus-interrupt bit is set if an interrupt is generated on the local bus.
interrupt-enable-mask register
Mask (bits 10 – 0)
Unused (bits 31 – 11)
The interrupt-enable-mask-register bit has a bit to correspond to every entry in the status register. When a bit
in the mask register is set, an interrupt is generated if a corresponding bit in the status register is also set.
BWG-table-configuration register
BWG Table Size (bits 10 – 0)
Unused (bits 31 – 11)
The 11-bit BWG-table-size register allows the user to configure the size of the BWG table in 4-byte words. Each
word in the table consists of four 8-bit entries. The maximum table size is 1200 decimal, allowing for 4800
entries. A resolution greater than 32 kb/s is achieved with 4800 entries. The number of entries in the table is
one more than the number programmed in this register; therefore, there is one entry in the table when the
register is set to zero.
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