參數(shù)資料
型號(hào)： TNETA1560
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 20/40頁(yè)
文件大?。?/td> 804K
代理商： TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit descriptor rings and DMA
Each transmit BWG is supported by a corresponding DMA channel and its own descriptor ring. The SBus SAR
supports 255 BWGs, 255 descriptor rings, and 255 DMA channels in the transmit direction. BWG 0 represents
null, indicating that an idle cell should be transmitted. This limits the number of packets and VCs active
simultaneously in the transmit direction to 255.
Each descriptor ring holds up to 256 entries corresponding to 256 buffers that may be queued for transmission
in the ring. The total number of buffers that can be queued for transmission by the device is 64K. The buffers
within a descriptor ring (each BWG) are serviced in FIFO order on a per-buffer basis. Each packet consists of
one or more byte-aligned buffers in host memory.
Each descriptor-ring entry contains a control bit that indicates whether a buffer is queued for transmission. The
DMA entry for each BWG contains a pointer to the first item in the queue in the corresponding descriptor ring.
An idle cell is transmitted if the control bit in the next entry of the descriptor ring indicates an inactive entry.
A field in each DMA entry allows the BWG to be disabled by the host. This may be used by the host to respond
to back-pressure mechanisms in software.
receive free-buffer rings and DMA
The SBus SAR uses buffer pointers from two free-buffer rings to place incoming packets in the host memory.
These are called small free-buffer ring and the big free-buffer ring. Each receive BWG has a control bit indicating
the type of buffer it uses: small or big. BWGs are unable to preallocate buffers for the next packet, which prevents
user processes from managing their own buffer space.
The SBus SAR supports 1023 receive DMA channels and 1023 VCs. The incoming VCI indexes the receive
DMA channels directly. BWG 0 is reserved to process special information for OAM cells. The drivers must
configure VCI 0 as a null-AAL VCI with a packet length equal to one cell.
completion rings
The SBus SAR indicates completion of packet processing in either direction to the host via an interrupt and by
posting entries to receive- and transmit-completion rings. Each completion ring accepts up to 256 entries. A
control bit in each entry of the completion ring prevents the device from overwriting an entry that has not been
processed by the host.
packet-size restrictions
The SBus SAR supports a maximum packet size of 64K bytes in either direction. The maximum buffer size for
transmit is also 64K bytes.
SBus interaction and burst-transfer size requirements
The SBus SAR behaves both as an SBus direct virtual memory access (DVMA) master and as a slave.
Table 2 classifies the interaction between the device and SBus into seven groups. This also quantifies the
support required from the DMA controller on the host machine.
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