參數(shù)資料
型號(hào)： TNETA1560
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 804K
代理商： TNETA1560
TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit modules
The transmit-host and buffer-transaction processor (XBTP) is responsible for all host-related functions on the
transmit side and requests 16- and 32-byte transfers from the SBus-interface block. The cell actuator accesses
the BWG table and determines the next VC to be serviced. The transmit adaptation-layer processor (XALP)
processes all AAL-related functions and adds the four bytes of the ATM header to each cell. The XALP identifies
the AAL5 CRC and determines if it should be appended to the packet. The transmit buffer (XMB) is an 8-cell
buffer that receives 13 words per cell. Idle cells are also placed in this buffer. The transmit PHY interface (XPIN)
does word-to-byte unpacking and interacts with the PHY layer using the SBus clock.
receive modules
The receive PHY interface (RPIN) performs byte-to-word packing, filters idle cells, and interacts with the PHY
layer using the system’s PHY-layer clock crystal. The receive buffer (RCB) performs rate synchronization from
the PHY-layer clock to the SBus clock and buffers up to 32 cells. The receive ATM processor (RAT) and the
receive ATM adaptation-layer processor (RALP) operate in parallel and are part of the same module. The RALP
terminates the AAL5 CRC and processes various EOP indicators. The RAT block is responsible for deleting the
ATM header and accessing the correct receive DMA entry. Finally, the receive host and buffer-transaction
processor (RBTP) performs all host-specific functions on the receive side.
SBus interface module
The SBus interface module (SBIN) is responsible for implementing the details of the SBus protocol. The XBTP
and the RBTP are the only two modules that require SBus transactions involving the SAR as a master; therefore,
SBIN arbitrates between requests from the two blocks. The SAR is the SBus slave when the host accesses
control memory, the local bus, or the user registers internal to the SAR.
control-memory interface and arbitration
The control-memory interface and arbitration (CMIA) block performs memory arbitration for all the blocks that
access control memory. Since each access is a 1-word access, no module can hold up the memory for a long
time. CMIA imposes a strict priority mechanism and services various blocks in the following order: RALP, XALP,
cell actuator, RBTP, SBTP, SBIN.
local bus-interface module
The local bus-interface (LBIN) module is used to access the EPROM and the registers on the PHY-layer device.
user register
The user-register block stores a number of configuration and operational registers. The user registers also
generate SBus interrupts on packet completion or when an error condition is detected.
data management
The SAR architecture uses two memory subsystems: host memory and on-board control memory. The control
memory provides fast multichannel memory-based DMA channels and a temporary storage area used as virtual
auxiliary registers. Some transmit and receive data-management components reside in control memory for
immediate access to critical real-time events isolated from host memory, which is tied to SBus latency. The AAL5
CRC is also encapsulated in the control memory. The control memory is accessible by the host for initialization
and monitoring the hardware and network status. Figure 15 shows the organization of the SAR data structures
across control and host memory.
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