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| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動柜員機(jī)分段和重組與SBus主機(jī)接口（自動柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 36/40頁 |
| 文件大小： | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
OWN (bit 31)
This completion-ring entry is owned by the SAR when the OWN bit is set and it is owned by the host when the
OWN bit is zero. If the OWN bit of the next entry in the respective receive completion ring is zero when the SAR
polls it to post the completion-of-packet processing, an error indicator in the status register is set and an interrupt
generated. This causes the buffer that the SAR attempted to post to be lost. The SAR clears the OWN bit in the
receive completion ring after it posts the packet. The host then owns the entry and may retrieve various pointers
to the packet.
packet overflow (bit 30)
The packet-overflow bit is set if the receive buffer overflowed while processing the current packet. Every packet
that ends in a buffer overflow is immediately terminated and a completion-ring entry is posted to the host.
CRC condition (bit 29)
The SAR forwards AAL5 packets with a CRC error to the host. This bit is set when a packet is received with
an AAL CRC error.
congestion cells received (bits 21 – 11)
The number of cells received in the packet with the EFCN indication set is forwarded to the host to implement
associated feedback mechanisms to squelch the source.
packet length (bits 10 – 0)
All received data is passed to the host in units of 48 bytes. The packet length in 48-byte payload units from
word 0 of the receive DMA block is passed to the host in two’s-complement notation. This value is always zero
for null-AAL packets. The length of AAL5 or AAL3/4 packets in integer units is obtained by subtracting this value
from the reassembly-buffer length reserved for the packet.
RX completion-ring word 1 – start-of-buffer pointer
Unused (bits 31 – 28) Start-of-buffer pointer – 16 byte aligned (bits 27 – 0)
The 28-bit start-of-buffer pointer is provided to the host in the RX completion ring to enable it to locate the
reassembled packet.
RX completion-ring word 2 – ATM header
ATM header byte 1
ATM header byte 2
ATM header byte 3
ATM header byte 4
The 4-byte header from the last cell in the reassembled packet is passed to the host.
user registers
This section describes several host-accessible internal SAR registers. Host-write accesses to nonexistent
registers are ignored. A null word (32 zeroes) is returned to the host on a read access from a nonexistent register.
configuration register
The configuration register holds various values pertaining to overall SAR configuration. The host may read the
register and is allowed to program the EN_RX and the EN_TX bits.
Unused (bits 31 – 5)
NCE_M (bit 4)
0 (bit 3)
EN_RX (bit 2)
EN_TX (bit 1)
0 (bit 0)
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