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參數(shù)資料
| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組與SBus主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
functional overview (continued)
The native clock for the SBus SAR is the SBus clock, which can range between 16.67 MHz and 25 MHz. The
8-bit-wide data path on the PHY-layer receive interface requires a clock rate of at least 19.44 MHz when
interacting with a 155.52 Mbit/s PHY-layer. The PHY-layer receive interface uses the the PHY-layer clock. The
native-word size for the device is 32 bits, corresponding to the data-bus width for SBus.
glossary and conventions
This section presents several special terms and conventions used throughout this document. It is not a complete
list of abbreviations.
transmit direction
The direction of data flow from SBus to the ATM PHY layer
receive direction
The direction of data flow from ATM PHY-layer to SBus
two’s-complement value
A number in two’s complement is given by (0 – actual positive value) modulo (2
n
), where n is the number of bits
in the field.
GFC
Generic flow control field. Appears in the upper four bits of the ATM cell header at the UNI.
EOM
End of message
EOP
End of packet
NCE
Network control engine
functional description
packet interface
The SBus SAR uses host memory to store the 48-byte payload units that constitute a packet in both the transmit
and receive directions. The device initiates the 48-byte data transfers containing packet data over the SBus for
both transmit and receive operations. The packet does not include AAL5 encapsulation while in host memory.
This is provided by the SBus SAR. The buffering within the device is limited to that required to match the
ATM-PHY transfer protocol to the transaction-oriented SBus transfer protocol. The chip contains an 8-cell
transmit FIFO and a 32-cell receive FIFO.
Each packet queued for transmission may be distributed across multiple buffers in host memory with each
starting at any byte boundary. This is supported in hardware by the device. Each received packet is placed in
a single buffer in host memory (either small or big) aligned to a 16-byte boundary.
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