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參數(shù)資料
| 型號： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 35/40頁 |
| 文件大?。?/td> | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
enable end-of-packet wait (bit 23)
When a start of a packet is detected by the TNETA1560, the TNETA1560 requests a buffer from the host
memory. If the buffer is not available, the first cell of this packet is dropped. The rest of the packet is dropped
after it is received. The host can set bit 23 to 1 enabling the TNETA1560 to drop the cells of a packet that had
the first cell dropped. Once the TNETA1560 detects the end packet, it begins to receive packets in this VCI. This
feature only works for AAL5 and AAL3/4. For null-AAL and OAM cells, bit 23 must be set to zero.
EFCN cell counter place holder (bits 21 – 11)
This field is set to zero since it is a place holder for the EFCN cell counter in word 0 of this DMA block.
AAL-packet length (bits 10 – 0)
The AAL-packet-length field in word 3 indicates the length of the buffer in cells for each packet in this BWG. This
is used in different ways based on whether the BWG supports AAL5 or AAL3/4 packets or null-AAL packets.
This field indicates the length of the buffer size allocated by entries in the free-buffer ring used by this BWG for
AAL5 or AAL3/4 packets. This is used to detect buffer overflow.
When the null-AAL indicator is set, this field programmed in two’s-complement notation represents the number
of cells in each null-AAL packet. Since receive DMA channel 0 operates off the null-AAL mode with each packet
of size equal to one cell, this field is programmed with the value 1 in two’s-complement notation (7FFhex).
RX DMA word 5 – AAL5 partial CRC
Partial AAL5 receive CRC (bits 31 – 0)
This field stores the 32-bit CRC that is calculated over the entire payload of each received AAL5 packet. The
CRC is stored in the last four bytes of the last cell in the AAL5 frame. The CRC check results in a unique
polynomial, if the frame is error free.
receive completion ring
Table 12 shows the composition of a 4-word receive completion-ring entry. The receive completion ring is a free
ring with 256 entries. The SAR posts an item to the next entry in the completion ring when it completes
reassembly on a packet. The receive-completion-ring pointer maintains the value of the current entry within the
SAR. The host can recalibrate to this by reading the value from the initialization section in control memory.
Table 12. Receive-Completion-Ring Summary
ENTRY
DESCRIPTION
Word 0
Control field, EFCN cells received, packet length
Word 1
Start-of-buffer pointer – 28 bits
Word 2
4-byte ATM header
Word 3
Reserved
RX completion-ring word 0 – control
Control (bits 31 – 29)
Congestion cells received (bits 21 – 11)
Packet length (bits 10 – 0)
Unused (bits 28 – 22)
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