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參數(shù)資料
| 型號(hào)： | TNETA1560 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with SBUS Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組與SBus主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁(yè)數(shù)： | 9/40頁(yè) |
| 文件大小： | 804K |
| 代理商： | TNETA1560 |
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TNETA1560
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH SBUS HOST INTERFACE
SDNS010C – JANUARY 1994 – REVISED OCTOBER 1995
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements (see Figure 3)
NO.
MIN
MAX
UNIT
1
tsu(SBBG)
tsu(SBACK)
th(SBACK)
Setup time, SBBG low before SBCLK
↑
15
ns
2
Setup time, SBACK2–SBACK0 valid before SBCLK
↑
15
ns
3
Hold time, SBACK2–SBACK0 valid after SBCLK
↑
0
ns
operating characteristics (see Figure 3)
NO.
4
5
6
7
MIN
MAX
UNIT
td(SBBR)
td(SBD)
td(SBRD)
td(SBSIZ)
Delay time, SBCLK
↑
to SBBR
↓
2.5
22
ns
Delay time, SBCLK
↑
to SBD31–SBD0 valid
2.5
22
ns
Delay time, SBCLK
↑
to SBRD
↓
2.5
22
ns
Delay time, SBCLK
↑
to SBSIZ2–SBSIZ0 valid
2.5
22
ns
The values are given for operation with a 25-MHz SBus clock.
3
SBCLK
(input)
SBBR
(output)
SBBG
(input)
SBD31–
SBD0
(output)
SBRD
(output)
SBSIZ2–
SBSIZ0
(output)
SBPA
(input)
SBACK2–
SBACK0
(input)
VA = Virtual address
4
1
5
6
7
2
Word 0
Word 1
Word 2
VA
3
3
3
3
7
7
7
7
7
Word 3
Figure 3. TNETA1560 Write Operation (TNETA1560 as Master in This Burst Operation)
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