參數(shù)資料
型號： XC3S400AN-5FTG256C
廠商： Xilinx Inc
文件頁數(shù)： 102/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標準包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計： 368640
輸入/輸出數(shù)： 195
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應商設備封裝： 256-FTBGA
Spartan-3AN FPGA Family: Introduction and Ordering Information
DS557 (v4.1) April 1, 2011
Product Specification
8
Ordering Information
Revision History
The following table shows the revision history for this document.
X-Ref Target - Figure 5
Figure 5: Device Numbering Format
Device
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ)
XC3S50AN
-4 Standard Performance TQ144/
TQG144
144-pin Thin Quad Flat Pack (TQFP)
C Commercial (0°C to 85°C)
XC3S200AN
-5 High Performance(1)
FT256/
FTG256
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
I
Industrial (–40°C to 100°C)
XC3S400AN
FG400/
FGG400
400-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S700AN
FG484/
FGG484
484-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S1400AN
FG676/
FGG676
676-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1.
The -5 speed grade is exclusively available in the Commercial temperature range.
2.
See Table 4 and Table 5 for available package combinations.
XC3S50AN -4 TQG144
C
Device Type
Speed Grade
Temperature Range:
Package Type/Number of Pins
Example:
DS557-1_05_101109
C = Commercial (T
J = 0
oC to 85oC)
I = Industrial (T
J = -40
oC to 100oC)
Date
Version
Revision
02/26/07
1.0
Initial release.
08/16/07
2.0
Updated for Production release of initial device.
09/12/07
2.0.1
Noted that only dual-mark devices are guaranteed for both -4I and -5C.
12/12/07
3.0
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
non-Pb-free packages may be available for selected devices.
06/02/08
3.1
Minor updates.
11/19/09
3.2
Updated document throughout to reflect availability of Pb package options. Added references to the
Extended Spartan-3A family. Removed table note 2 from Table 2. In Table 4, added Pb packages,
added table note 4, and updated table note 2. Added Table 5.
12/02/10
4.0
04/01/11
4.1
In Table 2, revised the Maximum Differential I/O Pairs and Maximum User I/O values for the
XC3S50AN. In Table 4, added packages to the XC3S50AN, XC3S400AN, and XC3S1400AN. Updated
Pb and Pb-Free Packaging section and Table 5 to include the new device/package combinations for
the XC3S50AN, XC3S400AN, and XC3S1400AN.
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相關代理商/技術參數(shù)
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