參數(shù)資料
型號: XC3S400AN-5FTG256C
廠商: Xilinx Inc
文件頁數(shù): 44/123頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3AN
LAB/CLB數(shù): 896
邏輯元件/單元數(shù): 8064
RAM 位總計: 368640
輸入/輸出數(shù): 195
門數(shù): 400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
27
Input Setup and Hold Times
Table 23: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Speed Grade
Units
-5
-4
Min
Setup Times
TIOPICK
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
No Input Delay is programmed.
LVCMOS25(2)
0
XC3S50AN
1.56
1.58
ns
XC3S200AN
1.71
1.81
ns
XC3S400AN
1.30
1.51
ns
XC3S700AN
1.34
1.51
ns
XC3S1400AN
1.36
1.74
ns
TIOPICKD
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
LVCMOS25(2)
1
XC3S50AN
2.16
2.18
ns
23.10
3.12
ns
33.51
3.76
ns
44.04
4.32
ns
53.88
4.24
ns
64.72
5.09
ns
75.47
5.94
ns
85.97
6.52
ns
1
XC3S200AN
2.05
2.20
ns
22.72
2.93
ns
33.38
3.78
ns
43.88
4.37
ns
53.69
4.20
ns
64.56
5.23
ns
75.34
6.11
ns
85.85
6.71
ns
1
XC3S400AN
1.79
2.02
ns
22.43
2.67
ns
33.02
3.43
ns
43.49
3.96
ns
53.41
3.95
ns
64.20
4.81
ns
74.96
5.66
ns
85.44
6.19
ns
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