Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
50
18 x 18 Embedded Multiplier Timing
Table 37: 18 x 18 Embedded Multiplier Timing
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Combinatorial Delay
TMULT
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
–4.36
–4.88
ns
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
–0.84
–1.30
ns
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
–4.44
–4.97
ns
Setup Times
TMSDCK_P
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
3.56
–3.98
–ns
TMSDCK_A
Data setup time at the A input before the active transition at the CLK
when using the AREG input register
(4)0.00
–0.00
–ns
TMSDCK_B
Data setup time at the B input before the active transition at the CLK
when using the BREG input register
(4)0.00
–0.00
–ns
Hold Times
TMSCKD_P
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
0.00
–0.00
–ns
TMSCKD_A
Data hold time at the A input after the active transition at the CLK
when using the AREG input register
(4)0.35
–0.45
–ns
TMSCKD_B
Data hold time at the B input after the active transition at the CLK
when using the BREG input register
(4)0.35
–0.45
–ns
Clock Frequency
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
0
280
0
250
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in
Table 10.
2.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3.
The PREG register is typically used when inferring a single-stage multiplier.
4.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5.
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.