DS557 (v4.1) April 1, 2011
Product Specification
12
Copyright 2007–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DC Electrical Characteristics
In this section, specifications can be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3AN devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Absolute Maximum Ratings
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
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Spartan-3AN FPGA Family:
DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
Table 6: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Max
Units
VCCINT
Internal supply voltage
–0.5
1.32
V
VCCAUX
Auxiliary supply voltage
–0.5
3.75
V
VCCO
Output driver supply voltage
–0.5
3.75
V
VREF
Input reference voltage
–0.5
VCCO +0.5
V
VIN
Voltage applied to all User I/O pins and
dual-purpose pins
Driver in a high-impedance state
–0.95
4.6
V
Voltage applied to all Dedicated pins
–0.5
4.6
V
IIK
Input clamp current per I/O pin
–0.5V < VIN < (VCCO + 0.5V)(1) –
±100
mA
VESD
Electrostatic Discharge Voltage
Human body model
–
±2000
V
Charged device model
–
±500
V
Machine model
–
±200
V
TJ
Junction temperature
–125
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1.
Upper clamp applies only when using PCI IOSTANDARDs.
1.
For soldering guidelines, see
UG112: Device Package User Guide and
XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free
Packages.